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TPS74001DPTR Datasheet(PDF) 6 Page - Texas Instruments |
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TPS74001DPTR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 25 page 1 2 3 4 8 7 6 5 GND EN/FB BIAS IN OUT GND GND GND 1 2 3 4 TAB DGKPACKAGE MSOP-8 (TOPVIEW) DPTPACKAGE JrS-PAK (TOPVIEW) 5 TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com PIN CONFIGURATION Table 1. TERMINAL FUNCTIONS TERMINAL DESCRIPTION DGK DPT NAME (MSOP-8) (Jr S-PAK) Enable pin; fixed output voltage version only. Driving this pin high enables the regulator; driving EN 1 1 this pin low puts the regulator into shutdown mode. This pin must not be left unconnected. Feedback pin; adjustable output voltage version only. The feedback connection to the center tap of FB 1 1 an external resistor divider network that sets the output voltage. This pin must not be left floating. BIAS 2 2 Bias input voltage for error amplifier, reference, and internal control circuits. IN 3 4 Input to the device. Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2 μF, ceramic) is needed OUT 4 5 from this pin to ground to assure stability. GND 5-8 3 Ground TAB TAB Internally connected to ground 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx |
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