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TPS75233QPWPR Datasheet(PDF) 7 Page - Texas Instruments |
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TPS75233QPWPR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 31 page www.ti.com V IN V res (1) V res t t t V OUT Threshold Voltage RESET Output 100ms Delay 100ms Delay Output Undefined Output Undefined V IT+ (2) Lessthan5%ofthe OutputVoltage V IT+ (2) V IT- (2) V IT- (2) V IN V PG (1) V PG V OUT V IT+ (2) V IT+ (2) V IT- (2) V IT- (2) t t t Output Undefined Output Undefined PG Output Threshold Voltage TPS752xxQ TPS754xxQ SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 TPS752xxQ RESET Timing Diagram (1) Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. (2) VIT: Trip voltage is typically 5% lower than the output voltage (95% VOUT). VIT– to VIT+ is the hysteresis voltage. TPS754xxQ Power Good Timing Diagram (1) VPG is the minimum input voltage for a valid Power Good. The symbol VPG is not currently listed within EIA or JEDEC standards for semiconductor symbology. (2) VIT: Trip voltage is typically 17% lower than the output voltage (83% VOUT). VIT– to VIT+ is the hysteresis voltage. Copyright © 2000–2007, Texas Instruments Incorporated Submit Documentation Feedback 7 |
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