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TPS84250RKGT Datasheet(PDF) 4 Page - Texas Instruments |
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TPS84250RKGT Datasheet(HTML) 4 Page - Texas Instruments |
4 / 29 page PWRGD VIN PGND PH VOUT RT/CLK VADJ STSEL SS/TR TPS84250 PWRGD Logic + + VREF Comp Power Stage and Control Logic Thermal Shutdown Shutdown Logic OCP VIN UVLO OSC w/PLL AGND INH/UVLO TPS84250 SLVSAR6 – AUGUST 2012 www.ti.com THERMAL INFORMATION TPS84250 THERMAL METRIC(1) RKG UNIT 41 PINS θJA Junction-to-ambient thermal resistance(2) 14 ψJT Junction-to-top characterization parameter(3) 3.3 °C/W ψJB Junction-to-board characterization parameter(4) 6.8 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance, θJA, applies to devices soldered directly to a 100 mm x 100 mm double-sided, 4-layer PCB with 1 oz. copper and natural convection cooling. Additional airflow reduces θJA. (3) The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TT is the temperature of the top of the device. (4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TB is the temperature of the board 1mm from the device. DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM 4 Copyright © 2012, Texas Instruments Incorporated |
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