BIT0

t

DIS(CSR-SDOZ)

t

H(SDI-SCLKR)

NOTE: CPOL=0,CPHA=0,Byte0cyclerequires24SCLKs,andByte1cyclerequires8SCLKs.

t

H(SCLKF-SDOVALID)

t

SU(SDI-SCLKR)

t

D(CSF-SDOVALID)

t

SU(SCLKF-CSR)

t

WH(CS)

t

C(SCLK)

t

SU(CSF-SCLK1R)

t

F

t

R

t

WL(SCLK)

t

WH(SCLK)

BIT1

MSBIN

MSBOUT

CS SS

(

)

SCLK

SDO(MISO)

SDI(MOSI)

BIT0

BIT1

CS

SCLK

PENIRQ/BUSY

(TSC2008)

t

D(SCLKR-PENIRQF)

t

SU(PENIRQR-SCLKR)

t

D(SCLKF-PENIRQF)

TSC2008-Q1

SBAS552

– JUNE 2011

www.ti.com

TIMING INFORMATION

The TSC2008-Q1 supports SPI programming in mode CPOL = 0 and CPHA = 0. The falling edge of SCLK is

used to change the output (MISO) data, and the rising edge is used to latch the input (MOSI) data. Eight SCLKs

are required to complete the command byte cycle, and an additional eight or 16 SCLKs are required for the data

to be read, depending on the mode used.

Figure 2. Detailed I/O Timing

Figure 3. PENIRQ Timing

6

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© 2011, Texas Instruments Incorporated