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SN74LVC1G126-EP Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVC1G126-EP Datasheet(HTML) 1 Page - Texas Instruments |
1 / 12 page SN74LVC1G126EP SINGLE BUS BUFFER GATE WITH 3STATE OUTPUT SCES527A − DECEMBER 2003 − REVISED MAY 2004 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Controlled Baseline − One Assembly/Test Site, One Fabrication Site D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† D Supports 5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 3.7 ns at 3.3 V † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. D Low Power Consumption, 10-µA Max ICC D ±24-mA Output Drive at 3.3 V D Ioff Supports Partial-Power-Down Mode Operation D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information This single bus buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G126 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING§ −40 °C to 85°C SOT (SC-70) − DCK Reel of 3000 CLVC1G126IDCKREP CN_ ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. § DCK: The actual top-side marking has one additional character that designates the assembly/test site. FUNCTION TABLE INPUTS OUTPUT OE A OUTPUT Y H H H H LL L X Z Copyright 2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DCK PACKAGE (TOP VIEW) 1 2 3 5 4 OE A GND VCC Y PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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