Background

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3

Sample 1% Resistor Values for Common LDO Output Voltages

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4

Bill of Materials

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1

Background

The Texas Instruments TPS54120 EVM (PWR103) helps design engineers evaluate the operation and

performance of the TPS54120 (Switcher + LDO) for possible use in their own circuit application. This

particular EVM configuration contains all of the external components required for a low noise 1A solution

with internal thermal and current limit shutdowns, and enable circuitry in a 3.5mm x 5.5mm, QFN,

thermally enhanced PowerPad

™ package.

The power input of the IC (PVIN) is rated for 1.6V to 17V while the control input (VIN) is rated for 4.5 to

17V. The TPS54120 provides both inputs but this EVM is designed and tested using the PVIN connected

to VIN with a minimum input voltage of 7V. Rated input voltage and output current range for the evaluation

module are given in Table 1. This evaluation module is designed to demonstrate the small

printed-circuit-board areas that may be achieved when designing with the TPS54120 device. The

switching frequency is externally set at a nominal 480 KHz.

The integrated switcher (SW) and LDO are optimized to allow the TPS54120 to achieve high efficiencies

and a low output noise. The compensation components are external to the integrated circuit (IC), and an

external divider allows for an adjustable LDO output voltage from 0.8V to 6V. Additionally, the TPS54120

provides adjustable slow start, tracking and enable inputs. The TPS54120, including other external

components that is capable of delivering up to 1A low noise supply to the load.

Table 1. EVM Specifications

EVM

Input Voltage

SW Output Voltage

LDO Output Voltage

Output Current

TPS54120

7-17V

4.1V

3.3V

0-1A

2

Setup

This section describes the jumpers and connectors on the EVM as well as how to properly connect, setup

and use the TPS54120EVM.

2.1

Input and Output Connections and Jumper Descriptions

•

J1-LDO OUT

& J2-GND: The output of the LDO and the ground connector. Default setting is 3.3V.

This is the low noise output from the TPS54120.

•

J3-VIN

& J4-GND: Input power supply voltage and the ground connector. The positive input lead and

ground return lead from the input power supply should be twisted and kept as short as possible to

minimize EMI transmission. Additional bulk capacitance should be added across J3

& J4 if the supply

leads are greater than six inches. For example, an additional 47

µF electrolytic capacitor across J3 & J4

can improve the transient response of the TPS54120 while eliminating unwanted ringing on the input

due to long wire connections.

•

J5: SMA connector for the output voltage of the LDO. The connector for J5 is not populated on the

TPS54120EVM (PWR103). This footprint allows the mounting of an SMA-style connector for more

accurate PSRR measurements.

•

J7-SW OUT

& J6-GND: The output of the SW and the ground connector. This is the output voltage

from the switcher converter and the input voltage to the LDO. Default setting is 4.1V

•

J8: SMA connector for the output voltage of the SW. The connector for J8 is not populated on the

TPS54120EVM (PWR103). This footprint allows the mounting of an SMA-style connector for more

accurate PSRR measurements.

•

JP1-LDOEN: LDO enable. To enable the output of the LDO, connect this jumper from the center pin to

the

“on” pin. This will connect the enable pin to the LDO input supply. To disable connect this jumper

from the center pin to the

“off” pin. This will short the LDO enable pin to ground.

•

JP2: The jumper connection between the output of the switcher converter to the LDO input. A shorting

jumper is required for normal operation. If you want to disconnect the LDO from the SW, remove the

shorting jumper wire.

2

TPS54120EVM, Low Noise 1A Power Supply Evaluation Module

SLVU641

– January 2012

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© 2012, Texas Instruments Incorporated