TLK2201JR

1.0 Gb to 1.6 Gb SMALL FORMFACTOR ETHERNET TRANSCEIVER

SCAS652F − AUGUST 2000 − REVISED MAY 2007

10

POST OFFICE BOX 655303

Terminal Functions (Continued)

TERMINAL

NAME

NO.

GQE

NO.

RCP†

I/O

DESCRIPTION

MODESEL

H3

15

I

P/D‡

Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR

interface. When low the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR

mode is selected. The default mode is the TBI.

TEST

LOOPEN

J2

19

I

P/D‡

Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The

transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test

capability in conjunction with the protocol device. The TXP and TXN outputs are held in a

high-impedance state during the loop-back test. LOOPEN is held low during standard

operational state with external serial outputs and inputs active.

JTCLK/TCK

H5

49

I

Test clock. IEEE1149.1 (JTAG)

JTDI

F8

48

I

P/U§

Test data input. IEEE1149.1 (JTAG)

JTDO

J5

27

O

Test data output. IEEE1149.1 (JTAG)

JTRSTN

E8

56

I

P/U§

Reset signal. IEEE1149.1 (JTAG)

JTMS

D8

55

I

P/U§

Test mode select. IEEE1149.1 (JTAG)

ENABLE

F2

28

I

P/U§

When this terminal is low, the device is disabled for Iddq testing. RD0−RD9, RBC, TXP, and

TXN are high-impedance. The pullup and pulldown resisters on any input are disabled.

When ENABLE is high, the device operates normally.

PRBSEN

H4

16

I

P/D§

PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS

verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive

inputs and checked for errors that are reported by the SYNC/PASS terminal indicating low.

TESTEN

H6

17

I

P/D‡

Manufacturing test terminal.

POWER

VDD

B8, C8,

G8, H8,

B2, C2,

D2, E2,

G2, H2

5, 10, 20,

23, 29,

37, 42,

50, 63

Supply

Digital logic power. Provides power for all digital circuitry and digital I/O buffers.

VDDA

B7, B6,

B5, B4

53, 57,

59, 60

Supply

Analog power. VDDA provides power for the high-speed analog circuits, receiver, and

transmitter

VDDPLL

B3

18

Supply

PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.

GROUND

GNDA

C7, D7,

C6, D6,

C5, D5, E5

51,58

Ground

Analog ground. GNDA provides a ground for the high-speed analog circuits, RX and TX.

GND

C4, D3,

D4, E3,

E4, E6, E7

F3, F4, F5,

F6, F7,

G3, G4,

G5, G6,

G7

1, 14, 21,

25, 33,

46

Ground

Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.

GNDPLL

N/A

64

Ground

PLL ground. Provides a ground for the PLL circuitry. Tied to GNDA in the GQE package.

† For cross reference to TLK2201 RCP package only.

‡ P/D = pulldown

§ P/U = pullup