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TM8FJ64NPU Datasheet(PDF) 11 Page - Texas Instruments |
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TM8FJ64NPU Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 24 page  TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64BIT EXTENDEDDATAOUT DYNAMIC RAM MODULES SODIMM SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997 11 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ac timing requirements (see Note 3) ’xxJ64xPU -40 ’xxJ64xPU - 50 ’xxJ64xPU - 60 UNIT MIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, read 69 84 104 ns tRWC Cycle time, read-write 92 111 135 ns tRASP Pulse duration, RASx active, page mode (see Note 7) 40 100 000 50 100 000 60 100 000 ns tRAS Pulse duration, RASx active, nonpage mode (see Note 7) 40 10 000 50 10 000 60 10 000 ns tRP Pulse duration, RASx precharge 25 30 40 ns tWP Pulse duration, write command 6 8 10 ns tASC Setup time, column address 0 0 0 ns tASR Setup time, row address 0 0 0 ns tDS Setup time, data in (see Note 8) 0 0 0 ns tRCS Setup time, read command 0 0 0 ns tCWL Setup time, write command before CASx precharge 6 8 10 ns tRWL Setup time, write command before RASx precharge 6 8 10 ns tWCS Setup time, write command before CASx active (early-write only) 0 0 0 ns tWRP Setup time, write before RASx active (CBR refresh only) 5 5 5 ns tCSR Setup time, CASx referenced to RASx (CBR refresh only) 5 5 5 ns tCAH Hold time, column address 6 8 10 ns tDH Hold time, data in (see Note 8) 6 8 10 ns tRAH Hold time, row address 6 8 10 ns tRCH Hold time, read command referenced to CASx (see Note 9) 0 0 0 ns tRRH Hold time, read command referenced to RASx (see Note 9) 0 0 0 ns tWCH Hold time, write command during CASx active (early-write only) 6 8 10 ns tRHCP Hold time, RASx active from CASx precharge 22 28 35 ns tOEH Hold time, OE0 command 11 13 15 ns tROH Hold time, RASx referenced to OE0 6 8 10 ns tWRH Hold time, write after RASx active (CBR refresh only) 6 8 10 ns tCHS Hold time, CASx active after RASx precharge (self-refresh) − 50 − 50 − 50 ns tAWD Delay time, column address to write command (read-write only) 35 42 49 ns tCHR Delay time, CASx referenced to RASx (CBR refresh only) 6 8 10 ns tCRP Delay time, CASx precharge to RASx 5 5 5 ns tCWD Delay time, CASx to write command (read-write operation only) 26 30 34 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 7. In a read-write cycle, tRWD and tRWL must be observed. 8. Referenced to the later of CASx or WE0 in write operations 9. Either tRRH or tRCH must be satisfied for a read cycle. |
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