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TM8SK64KPU Datasheet(PDF) 10 Page - Texas Instruments |
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TM8SK64KPU Datasheet(HTML) 10 Page - Texas Instruments |
10 / 17 page TM4SK64KPU 4194304 BY 64BIT TM8SK64KPU 8388608 BY 64BIT SYNCHRONOUS DYNAMIC RAM MODULES SODIMM SMMS691A − AUGUST 1997 − REVISED NOVEMBER 1997 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 clock timing requirements† ’xSK64KPU-10 ’xSK64KPU-12 UNIT‡ MIN MAX MIN MAX UNIT‡ tREF Refresh interval 64 64 ms tREF Refresh interval 64 64 ms nCCD Delay time, READ or WRT command to an interrupting command 1 1 cycles nCCD Delay time, READ or WRT command to an interrupting command 1 1 cycles nCDD Delay time, CS low or high to input enabled or inhibited 0 0 0 0 cycles nCLE Delay time, CKE high or low to CLK enabled or disabled 1 1 1 1 cycles nCWL Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P 1 1 cycles nDID Delay time, ENBL or MASK command to enabled or masked data in 0 0 0 0 cycles nDOD Delay time, ENBL or MASK command to enabled or masked data out 2 2 2 2 cycles nHZP2 Delay time, DEAC or DCAB, command to DQ in high−impedance state CAS latency = 2 2 2 cycles nHZP3 Delay time, DEAC or DCAB, command to DQ in high−impedance state CAS latency = 3 3 3 cycles nWCD Delay time, WRT command to first data in 0 0 0 0 cycles † All references are made to the rising transition of CK unless otherwise noted. ‡ A CK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated by CKE (those CK cycles occurring during the time when CKE is asserted low). |
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