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TM8SP64KPU Datasheet(PDF) 8 Page - Texas Instruments |
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TM8SP64KPU Datasheet(HTML) 8 Page - Texas Instruments |
8 / 18 page TM4SP64KPU 4194304 BY 64BIT TM8SP64KPU 8388608 BY 64BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS689 − AUGUST 1997 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3) TM8SP64KPU PARAMETER TEST CONDITIONS ’8SP64KPU-10 ’8SP64KPU-12 UNIT PARAMETER TEST CONDITIONS MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = − 2 mA 2.4 2.4 V VOL Low-level output voltage IOL = 2 mA 0.4 0.4 V II Input current (leakage) 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD "20 "20 µA IO Output current (leakage) 0 V < VO < VDD +0.3 V, Output disabled "20 "20 µA ICC1 Operating current Burst length = 1, tRC ≥ tRC MIN CAS latency = 2 488 468 mA ICC1 Operating current tRC ≥ tRC MIN IOH/IOL = 0 mA (See Notes 4, 5, and 6) CAS latency = 3 548 488 mA ICC2P Precharge standby current in CKE ≤ VIL MAX, tCK = 15 ns (see Note 7) 16 16 mA ICC2PS Precharge standby current in power-down mode CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 8) 16 16 mA ICC2N Precharge standby current in CKE ≥ VIH MIN, tCK = 15 ns (see Note 7) 320 320 mA ICC2NS Precharge standby current in non-power-down mode tCK = ∞ (see Note 8) 24 24 mA ICC3P Active standby current in CKE ≤ VIL MAX, tCK = 15 ns (see Notes 4 and 7) 80 80 mA ICC3PS Active standby current in power-down mode CKE and CK ≤ VIL MAX, tCK = ∞ (see Notes 4 and 8) 80 80 mA ICC3N Active standby current in CKE ≥ VIH MIN, tCK = 15 ns (see Notes 4 and 7) 560 520 mA ICC3NS Active standby current in non-power-down mode CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞ (see Notes 4 and 8) 160 160 mA ICC4 Burst current Page burst, IOH/IOL = 0 mA All banks activated, CAS latency = 2 588 568 mA ICC4 Burst current All banks activated, nCCD = one cycle (see Notes 9 and 10) CAS latency = 3 868 728 mA ICC5 Auto-refresh current tRC ≤ tRC MIN CAS latency = 2 668 648 mA ICC5 Auto-refresh current tRC ≤ tRC MIN (see Notes 5 and 8) CAS latency = 3 788 648 mA ICC6 Self-refresh current CKE ≤ VIL MAX 16 16 mA NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Only one bank is activated. 5. tRC w MIN 6. Control, DQ, and address inputs change state twice during tRC. 7. Control, DQ, and address inputs change state once every 30 ns. 8. Control, DQ, and address inputs do not change. 9. Control, DQ, and address inputs change once every cycle. 10. Continuous burst access, nCCD = 1 cycle |
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