15

12

11

8

7

6

5

4

1

0

TMS34094

ISA BUS INTERFACE

SPVS006A – FEBRUARY 1992 – REVISED JUNE 1992

POST OFFICE BOX 1443

10

Each 32-bit BKMSKx register is accessed via the BKPORT register as two 16-bit halves, BKMSKxL and

BKMSKxH. The BPNT3–BPNT0 bits of the BKCTL register select which bank select register is accessed during

a read or write of BKPORT.

Host write accesses to BKMSK0–BKMSK3 may cause improper decode of ongoing TMS34020 local bus cycles.

Do not write to any BKMSK0–BKMSK3 register when the TMS34020 is performing any operation which could

be adversely affected by improper address decoding, including execution of code, may cause improper decode

of ongoing TMS34020 local bus cycles.

BKCTL

BVEN3–BVEN0

BDRD3–BDRD0

RM1–RM0

ABE

BPNT3–BPNT0

This register contains several bits which control how the TMS34094 decodes LAD bus cycles for bank select

operations.

BVEN3–BVEN0 are individual VRAM selectors for each bank. If a memory bank contains VRAM, it should

respond to write mask load or color register load cycles generated by the TMS34020. Setting BVENn to a 1

causes BSELn to be asserted whenever one of these special VRAM cycles occur. BVEN3–BVEN0 are cleared

after reset.

BDRD3–BDRD0 are individual DRAM refresh deselectors for each bank. If a bank does not require refresh, the

corresponding bit in BDRD3–BDRD0 should be set to 1. This will cause the corresponding bank select signal

to ignore DRAM refresh cycles generated by the TMS34020. These bits are cleared after reset.

RM1–RM0 determines how the DRAM refresh cycles generated by the TMS34020 should affect the bank select

signals as summarized in the table below. If the memory banks are to be refreshed alternately, the TMS34094

determines which bank is refreshed using the values on LAD16 and LAD17. RM1–RM0 are cleared after reset.

RM1

RM0

FUNCTION

0

0

1

1

0

1

0

1

Refresh all banks simultaneously

Refresh alternate pairs

Refresh one bank at a time

No refresh

ABE enables all bank select operations. After reset, ABE is set to 0 causing BSEL3 to be unconditionally low

and all other bank select signals to be inactive (high) except for memory refresh. Setting ABE to 1 allows the

bank select signals to decode local addresses from the TMS34020.