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TMS417800A-60DZ Datasheet(PDF) 9 Page - Texas Instruments |
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TMS417800A-60DZ Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 24 page  TMS417800A 2097152 BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS888B – AUGUST 1996 – REVISED SEPTEMBER 1997 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ac timing requirements (see Note 4) (continued) ’417800A - 50 ’417800A - 60 ’417800A - 70 UNIT MIN MAX MIN MAX MIN MAX UNIT tCHR Delay time, CAS referenced to RAS (CBR refresh only) 10 10 10 ns tCRP Delay time, CAS precharge to RAS 5 5 5 ns tCSH Delay time, RAS active to CAS precharge 50 60 70 ns tCWD Delay time, CAS to write command (read-write operation only) 36 40 46 ns tOED Delay time, OE to data in 13 15 18 ns tRAD Delay time, RAS to column address (see Note 11) 13 25 15 30 15 35 ns tRAL Delay time, column address to RAS precharge 25 30 35 ns tCAL Delay time, column address to CAS precharge 25 30 35 ns tRCD Delay time, RAS to CAS (see Note 11) 18 37 20 45 20 52 ns tRPC Delay time, RAS precharge to CAS 5 5 5 ns tRSH Delay time, CAS active to RAS precharge 13 15 18 ns tRWD Delay time, RAS to write command (read-write operation only) 73 85 98 ns tCPW Delay time, CAS precharge to write command (read-write only) 53 60 68 ns tREF Refresh time interval 32 32 32 ms tT Transition time 2 30 2 30 2 30 ns NOTES: 4. With ac parameters, it is assumed tT = 5 ns. 11. The maximum value is specified only to ensure access time. PARAMETER MEASUREMENT INFORMATION VTH VCC CL = 100 pF (see Note A) Output Under Test Output Under Test CL = 100 pF (see Note A) (b) ALTERNATE LOAD CIRCUIT (a) LOAD CIRCUIT NOTE A: CL includes probe and fixture capacitance. RL R1 R2 DEVICE VCC (V) R1 (W) R2 (W) VTH (V) RL (W) ’417800A 5 828 295 1.31 218 Figure 1. Load Circuits for Timing Parameters |
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