TMS417809A, TMS427809A, TMS427809AP

2097152 BY 8-BIT EXTENDED DATA OUT

DYNAMIC RANDOM-ACCESS MEMORIES

SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997

4

POST OFFICE BOX 1443

write-enable ( W )

The read- or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects

the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS

(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with

OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled as long as CAS is high

(see Figure 8).

data in / data out (DQ0 – DQ7)

Data is written during a write- or read-modify-write cycle. Depending on the mode of operation, the latter of the

falling edges of CAS or W strobes data into the on-chip data latch with setup-and-hold times referenced to the

latter edge. The DQs drive valid data after all access times are met and the data remains valid except in cases

described in the W and OE descriptions.

RAS-only refresh

A refresh operation must be performed once every 32 ms (128 ms for TMS427809AP) to retain data. This can

be achieved by strobing each of the 2 048 rows (A0 – A10). A normal read- or write cycle refreshes all bits in each

row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving

power as the output buffers remain in the high-impedance state. Externally generated addresses must be used

for a RAS-only refresh.

hidden refresh

A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by

RAS-only refresh cycle. The external address is ignored and the refresh address is generated internally.

CAS-before-RAS ( CBR ) refresh

The external address is ignored and the refresh address is generated internally.

battery-backup refresh

TMS427809AP

A low-power battery-backup refresh mode that requires less than 350

mA of refresh current is available on the

TMS427809AP. Data integrity is maintained using CBR refresh with a period of 62.5

ms while holding RAS low

for less than 300 ns. To minimize current consumption, all input levels must be at CMOS levels

self-refresh (TMS427809AP)

The self-refresh mode is entered by dropping CAS low prior to RAS going low, then CAS and RAS are both held

low for a minimum of 100

ms. The chip is refreshed internally by an on-board oscillator. No external address is

required because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS

of row addresses) must be executed before continuing with normal operation to ensure that the DRAM is fully

refreshed.

power up

To achieve proper device operation, an initial pause of 200

µs followed by a minimum of eight initialization cycles

( RAS-only or CBR ) cycle.