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TNETE100PCE Datasheet(PDF) 11 Page - Texas Instruments |
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TNETE100PCE Datasheet(HTML) 11 Page - Texas Instruments |
11 / 26 page ThunderLAN ™ TNETE100 PCI ETHERNET ™ CONTROLLER SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN ™ SPWS017B – APRIL 1995 – REVISED AUGUST 1996 11 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 10 Base-T physical layer (continued) TNETE100 PCI FXMTP FXMTN FRCVP FRCVN RJ-45 Figure 2. Schematic for 10 Base-T Network Interface Using TNETE100 FIFO pointer registers (FPREGS) The FPREGS are used to implement circular buffer FIFOs in the SRAM. They are a collection of pointer and counter registers used to maintain the FIFO operation. Both the PCIIF and PH use FPREGS to determine where to read or write data in the SRAM and to determine how much data the FIFO contains. Unique receive and transmit FIFO registers are needed for each data channel supported. FIFO SRAM (FSRAM) The FSRAM is a conventional SRAM array accessed synchronously to the PCI bus clock. Access to the RAM is allocated on a time-division multiplexed (TDM) basis, rather than through a conventional shared bus. This removes the need for bus arbitration and provides guaranteed bandwidth. Half the RAM accesses (every other cycle) are allocated to the PCI controller. It has a 64-bit access port to the RAM, giving it 1 Gbps of bandwidth, sufficient to support 32-bit data streaming on the PCI bus. The PH has one-quarter the RAM accesses, and its port may be up to 64 bits wide. A 64-bit port for the PH provides 512 Mbps of bandwidth, more than sufficient for a full-duplex 100-Mbps network. The remaining RAM accesses can be allocated toward providing even more PH bandwidth. The RAM is also accessible (for diagnostic purposes) from the TNETE100 internal data bus. Host DIO (mapped I / O) accesses are used by the host to access internal TNETE100 registers and for adapter test. D 3.375K bytes of FSRAM – 1.5K-byte FIFO for receive – Two 0.75K-byte FIFOs for the two transmit channels – Three 128-byte lists D In one-channel mode, the two transmit channels are combined giving a single 1.5K-byte FIFO for a single transmit channel. Supporting 1.5K bytes of FIFO per channel allows full frame buffering of Ethernet frames. PCI latency is such that a minimum of 500 bytes of storage is required to support 100-Mbps LANs. test-access port (TAP) Compliant with IEEE Standard 1149.1, the TAP is comprised of five pins that are used to interface serially with the device and with the board on which it is installed for boundary-scan testing. |
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