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TNETE110 Datasheet(PDF) 7 Page - Texas Instruments |
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TNETE110 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 24 page ThunderLAN ™ TNETE110 PCI ETHERNET ™ CONTROLLER SINGLE-CHIP 10 BASE-T SPWS018B – MARCH 1995 - REVISED MAY 1996 7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Functions (Continued) PIN TYPE† DESCRIPTION NAME NO. TYPE† DESCRIPTION PCI INTERFACE (CONTINUED) PREQ 134 I/O PCI bus request. PREQ is asserted by the TNETE110 to request control of the PCI bus. This is not a shared signal. PRST 129 I PCI reset signal PSERR 25 O/D PCI system error. PSERR indicates parity errors or special-cycle data-parity errors. PSTOP 23 I/O PCI stop. PSTOP indicates the current target is requesting the master to stop the current transaction. BIOS ROM / LED DRIVER INTERFACE EAD7 EAD6 EAD5 EAD4 EAD3 EAD2 EAD1 EAD0 54 55 56 57 59 60 61 62 I/O EPROM address / data. EAD[0 –7] is a multiplexed byte bus that is used to address and to read data from an external BIOS ROM. • On the cycle when EXLE is asserted low, EAD[0–7] is driven with the high byte of the address. • On the cycle when EALE is asserted low, EAD[0–7] is driven with the low byte of the address. • When EOE is asserted, BIOS ROM data should be placed on the bus. These pins can be used also to drive external status LEDs. Low-current (2 – 5 mA) LEDs can be connected directly through appropriate resistors. High-current LEDs can be driven through buffers or from the BIOS ROM address latches. EALE 65 O EPROM address latch enable. EALE is driven low to latch the low (least significant) byte of the BIOS ROM address from EAD[0 –7]. EOE 64 O EPROM output enable. When EOE is active (low), EAD[0 –7] is 3-stated and the output of the BIOS ROM should be placed on EAD[0 –7]. EXLE 66 O EPROM extended address-latch enable. EXLE is driven low to latch the high (most significant) byte of the BIOS ROM address from EAD[0 –7]. CONFIGURATION EEPROM INTERFACE EDCLK 68 O EEPROM data clock. EDCLK transfers serial clocked data to the 2K-bit serial EEPROMs (24C02) (see Note 1). EDIO 69 I/O EEPROM data I / O. EDIO is the bidirectional serial data / address line to the 2K-bit serial EEPROM (24C02). EDIO requires an external pullup for EEPROM operation. Tying EDIO to ground disables the EEPROM interface and prevents autoconfiguration of the PCI configuration register. MANAGEMENT DATA PINS MDCLK 91 O Management data clock. MDCLK is part of the serial management interface to physical-media independent (PMI)/PHY chip. MDIO 93 I/O Management data I / O. MDIO is part of the serial management interface to PMI/PHY chip. NETWORK INTERFACE (10 Base-T AND AUI) ACOLN ACOLP 111 109 A AUI receive pair. ACOLN and ACOLP are differential line receiver inputs and connect to the receive pair through transformer isolation, etc. ARCVN ARCVP 108 106 A AUI receive pair. ARCVN and ARCVP are differential line receiver inputs and connect to the receive pair through transformer isolation, etc. AXMTP AXMTN 99 100 A AUI transmit pair. AXMTP and AXMTN are differential line transmitter outputs. FATEST 118 A Analog test pin. FATEST provides access to the filter of the reference PLL. This pin must be left as a no connect. FIREF 116 A Current reference. FIREF is used to set a current reference for the analog circuitry. † I = input, O = output, I / O = 3-state input / output, O / D = open-drain output, A = analog NOTE 1: This pin should be tied to VDD with a 4.7-kW – 10-kW pullup resistor. |
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