TSB12LV26TPZEP datasheet(5/85 Pages) TI1

Part #	TSB12LV26TPZEP

Description	OHCI-LYNX PCI-BASED IEEE 1394 HOST CONTROLLER

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Manufacturer	TI1 [Texas Instruments]

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5 / 85 page

vi

4−1

OHCI Register Map

4−1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−2

OHCI Version Register Description

4−4

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−3

GUID ROM Register Description

4−5

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−4

Asynchronous Transmit Retries Register Description

4−6

. . . . . . . . . . . . . . . .

4−5

CSR Control Register Description

4−7

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−6

Configuration ROM Header Register Description

4−8

. . . . . . . . . . . . . . . . . . . .

4−7

Bus Options Register Description

4−9

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−8

Configuration ROM Mapping Register Description

4−11

. . . . . . . . . . . . . . . . . . .

4−9

Posted Write Address Low Register Description

4−11

. . . . . . . . . . . . . . . . . . . .

4−10

Posted Write Address High Register Description

4−12

. . . . . . . . . . . . . . . . . . . .

4−11

Host Controller Control Register Description

4−13

. . . . . . . . . . . . . . . . . . . . . . . .

4−12

Self-ID Count Register Description

4−15

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−13

Isochronous Receive Channel Mask High Register Description

4−16

. . . . . . .

4−14

Isochronous Receive Channel Mask Low Register Description

4−17

. . . . . . . .

4−15

Interrupt Event Register Description

4−18

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−16

Interrupt Mask Register Description

4−20

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−17

Isochronous Transmit Interrupt Event Register Description

4−22

. . . . . . . . . . .

4−18

Isochronous Receive Interrupt Event Register Description

4−24

. . . . . . . . . . .

4−19

Fairness Control Register Description

4−25

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−20

Link Control Register Description

4−26

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−21

Node Identification Register Description

4−27

. . . . . . . . . . . . . . . . . . . . . . . . . . .

4−22

PHY Control Register Description

4−28

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−23

Isochronous Cycle Timer Register Description

4−29

. . . . . . . . . . . . . . . . . . . . . .

4−24

Asynchronous Request Filter High Register Description

4−30

. . . . . . . . . . . . .

4−25

Asynchronous Request Filter Low Register Description

4−32

. . . . . . . . . . . . . .

4−26

Physical Request Filter High Register Description

4−33

. . . . . . . . . . . . . . . . . . .

4−27

Physical Request Filter Low Register Description

4−35

. . . . . . . . . . . . . . . . . . .

4−28

Asynchronous Context Control Register Description

4−36

. . . . . . . . . . . . . . . . .

4−29

Asynchronous Context Command Pointer Register Description

4−37

. . . . . . .

4−30

Isochronous Transmit Context Control Register Description

4−38

. . . . . . . . . .

4−31

Isochronous Receive Context Control Register Description

4−39

. . . . . . . . . . .

4−32

Isochronous Receive Context Match Register Description

4−42

. . . . . . . . . . . .

6−1

Registers and Bits Loadable Through Serial ROM

6−1

. . . . . . . . . . . . . . . . . . .

6−2

Serial ROM Map

6−2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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