Rev 2.1 ©2012 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, CA 94089-1706 Tel: (408) 747-1155 Fax: (408) 747-1286

www.aldinc.com

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GENERAL DESCRIPTION

ALD110800A/ALD110800/ALD110900A/ALD110900 are high precision

monolithic quad/dual N-Channel MOSFETs matched at the factory using

ALD’s proven EPAD CMOS technology. These devices are members of

Intended for low voltage small signal applications, the ALD110800/

ALD110900 features Zero-Threshold

nates input to output voltage level shift, including circuits where the signal

is referenced to GND or V+. This feature greatly reduces output signal

voltage level shift and enhances signal operating range, especially for

very low operating voltage environments. With these zero threshold de-

vices, an analog circuit with multiple stages can be constructed to oper-

ate at extremely low supply or bias voltage levels. For example, an input

amplifier stage operating at 0.2V supply voltage has been demonstrated.

ALD110800A/ALD110800/ALD110900A/ALD110900 matched pair

MOSFETs are designed for exceptional device electrical characteristics

matching with the threshold voltage set precisely at +0.00V +0.01V, fea-

turing a typical offset voltage of only +0.001V (1mV). As these devices

are on the same monolithic chip, they also exhibit excellent tempco track-

ing characteristics. They are versatile as design components for a broad

range of analog applications such as basic building blocks for current

sources, differential amplifier input stages, transmission gates, and multi-

plexer applications.

Besides matched pair electrical characteristics, each individual MOSFET

also exhibits well controlled parameters, enabling the user to depend on

tight design limits. Even units from different batches and different date

of manufacture have correspondingly well matched characteristics.

These devices are built for minimum offset voltage and differential ther-

mal response, and they are designed for switching and amplifying appli-

cations in +0.2V to +10V systems where low input bias current, low input

devices is set at +0.00V, which classifies them as both enhancement mode

and depletion mode devices. When the gate is set at 0.00V, the drain

voltage level biased at or near input voltage level without voltage level

shift. These devices exhibit well controlled turn-off and sub-threshold

characteristics of standard enhancement mode MOSFETs.

The ALD110800A/ALD110800/ALD110900A/ALD110900 are MOSFET

gain (>10

of 3mA and input leakage current of 30pA at 25°C is 3mA/30pA =

100,000,000. For most applications, connect the V+ pin to the most posi-

tive voltage and the V- and IC pins to the most negative voltage in the

system. All other pins must have voltages within these voltage limits at all

times.

PRECISION MATCHED PAIR MOSFET ARRAY

FEATURES

• Precision zero threshold voltage mode

• Matched MOSFET to MOSFET characteristics

• Tight lot to lot parametric control

• Low input capacitance

• Low input/output leakage currents

APPLICATIONS

• Energy harvesting circuits

• Very low voltage analog and digital circuits

• Zero power fail safe circuits

• Backup battery circuits & power failure detector

• Low level voltage clamp & zero crossing detector

• Source followers and buffers

• Precision current mirrors and current sources

• Capacitives probes and sensor interfaces

• Charge detectors and charge integrators

• Differential amplifier input stage

• High side switches

• Peak detectors and level shifters

• Sample and Hold

• Current multipliers

• Analog switches / multiplexers

• Voltage comparators and level shifters

ALD110800/ALD110800A/ALD110900/ALD110900A

* Contact factory for industrial temp. range or user-specified threshold voltage values.

Operating Temperature Range*

0°C to +70°C0°C to +70°C

16-Pin

16-Pin

8-Pin

8-Pin

SOIC

Plastic Dip

SOIC

Plastic Dip

Package

Package

Package

Package

ALD110800ASCL

ALD110800APCL

ALD110900ASAL

ALD110900APAL

ALD110800SCL

ALD110800PCL

ALD110900SAL

ALD110900PAL

*IC pins are internally connected, connect to V-

SCL, PCL PACKAGES

PIN CONFIGURATIONS

SAL, PAL PACKAGES

VGS(th)= +0.00V

IC*

1

2

3

14

15

16

4

13

5

12

IC*

6

7

8

10

11

IC*

IC*

9

M 4

M 3

M 1

M 2

V-

1

2

3

6

7

8

4

5

M 1

M 2

V-

V-

V-

IC*

IC*

ALD110800

ALD110900