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PC16552D Datasheet(PDF) 9 Page - Texas Instruments |
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PC16552D Datasheet(HTML) 9 Page - Texas Instruments |
9 / 24 page 40 Timing Waveforms All timings are referenced to valid 0 and valid 1 (Continued) RCVR FIFO First Byte (This Sets RDR) TLC9426 – 10 RCVR FIFO Bytes Other Than the First Byte (RDR Is Already Set) TLC9426 – 11 Receiver Ready FCR0 e 0 or FCR0 e 1 and FCR3 e 0 (Mode 0) TLC9426 – 12 Note 1 This is the reading of the last byte in the FIFO Note 2 If FCR0 e 1 then tSINT e 3 RCLKs For a timeout interrupt tSINT e 8 RCLKs 8 |
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