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S25FL129P Datasheet(PDF) 11 Page - SPANSION |
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S25FL129P Datasheet(HTML) 11 Page - SPANSION |
11 / 69 page September 21, 2012 S25FL129P_00_08 S25FL129P 11 Data Sheet 3. Input/Output Descriptions 4. Logic Symbol Signal I/O Description SO/IO1 I/O Serial Data Output: Transfers data serially out of the device on the falling edge of SCK. Functions as an I/O pin in Dual and Quad I/O, and Quad Page Program modes. SI/IO0 I/O Serial Data Input: Transfers data serially into the device. Device latches commands, addresses, and program data on SI on the rising edge of SCK. Functions as an I/O pin in Dual and Quad I/O mode. SCK Input Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI on rising edge of SCK. Triggers output on SO after the falling edge of SCK. CS# Input Chip Select: Places device in active power mode when driven low. Deselects device and places SO at high impedance when high. After power-up, device requires a falling edge on CS# before any command is written. Device is in standby mode when a program, erase, or Write Status Register operation is not in progress. HOLD#/IO3 I/O Hold: Pauses any serial communication with the device without deselecting it. When driven low, SO is at high impedance, and all input at SI and SCK are ignored. Requires that CS# also be driven low. Functions as an I/O pin in Quad I/O mode. W#/ACC/IO2 I/O Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When driven low, prevents any program or erase command from altering the data in the protected memory area. Functions as an I/O pin in Quad I/O mode. VCC Input Supply Voltage GND Input Ground CS# SO/IO1 W#/ACC/IO2 GND SI/IO0 SCK HOLD#/IO3 VCC |
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