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SN74ALVC16270DLR Datasheet(PDF) 1 Page - Texas Instruments

Part # SN74ALVC16270DLR
Description  12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN74ALVC16270DLR Datasheet(HTML) 1 Page - Texas Instruments

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(TOP VIEW)
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OEA
CLKEN1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
CLKEN2B
SEL
OEB
CLKENA2
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
CLKENA1
CLK
SN74ALVC16270
12BIT TO 24BIT REGISTERED BUS EXCHANGER
WITH 3STATE OUTPUTS
SCAS433A − OCTOBER 1993 − REVISED JULY 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
D EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
D Member of the Texas Instruments
Widebus
 Family
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D Bus Hold on Data Inputs Eliminates
the Need for External Pullup/Pulldown
Resistors
D Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
The SN74ALVC16270 is a 12-bit to 24-bit
registered bus exchanger, which is intended for
use
in
applications
where
data
must
be
transferred from a narrow high-speed bus to a
wide
lower-frequency
bus.
This
device
is
designed specifically for low-voltage (3.3-V) VCC
operation.
The device provides synchronous data exchange
between the two ports. Data is stored in the
internal registers on the low-to-high transition of
the clock (CLK) input when the appropriate
CLKEN inputs are low. The select (SEL) line
selects 1B or 2B data for the A outputs. For data
transfer in the A-to-B direction, a two-stage
pipeline
is
provided
in
the
A-to-1B
path,
with a single storage register in the A to 2B path. Proper control of the CLKENA inputs allows two sequential
12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the
active-low output enables (OEA, OEB). The control terminals are registered to synchronize the bus direction
changes with CLK.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVC16270 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed-circuit-board area.
The SN74ALVC16270 is characterized for operation from − 40
°C to 85°C.
Copyright
 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.


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