TLC55025M

8BIT ANALOGTODIGITAL CONVERTER

SGLS067 − MARCH 1992

POST OFFICE BOX 655303

4−180

functional block diagram

D0 (LSB)

D1

D2

D3

D4

D5

D6

D7 (MSB)

REFB

REFM

REFT

ANLG INPUT

CLK

Buffer

and

Latch

Encoder

255-to-8

EN

R1

R

R

R2

R

R

255

254

128

R/2

R/2

127

2

1

10

19, 20

17

18

21

9

8

7

6

5

4

3

2

operating sequence

D0−D7

INPUT

ANALOG

CLK

td

N+1

Data

N

Data

N−1

Data

N + 2

Sample

N + 1

Sample

N

Sample

Following the operating sequence above, the rising edge of the clock samples the analog input (sample N) at

acquires sample N + 1. Conversion is completed in one clock cycle and continues the sequence for the next

cycle.