TLC542C, TLC542I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 INPUTS

SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001

9

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

The TLC542 is a complete data acquisition system on a single chip. The device includes such functions as analog

multiplexer, sample and hold, 8-bit A/D converter, data and control registers, and control logic. Three control inputs

(I/O CLOCK, CS (chip select), and ADDRESS INPUT) are included for flexibility and access speed. These control

inputs and a TTL-compatible 3-state output are intended for serial communications with a microprocessor or

microcomputer. With judicious interface timing, the TLC542 can complete a conversion in 20

µs, while complete

input-conversion-output cycles can be repeated every 40

µs. Furthermore, this fast conversion can be executed on

any of 11 inputs or its built-in self-test and in any order desired by the controlling processor.

When CS is high, the DATA OUT terminal is in a 3-state condition, and the ADDRESS INPUT and I/O CLOCK

terminals are disabled. When additional TLC542 devices are used, this feature allows each of these terminals, with

the exception of the CS terminal, to share a control logic point with their counterpart terminals on additional A/D

devices. Thus, this feature minimizes the control logic terminals required when using multiple A/D devices.

The control sequence is designed to minimize the time and effort required to initiate conversion and obtain the

conversion result. A normal control sequence is as follows:

1.

CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for two

rising edges and then a falling edge of the internal system clock before recognizing the low CS transition.

The MSB of the result of the previous conversion automatically appears on the DATA OUT terminal.

2.

On the first four rising edges of the I/O CLOCK, a new positive-logic multiplexer address is shifted in, with

the MSB of this address shifted first. The negative edges of these four I/O CLOCK pulses shift out the

second, third, fourth, and fifth most significant bits of the result of the previous conversion. The on-chip

sample and hold begins sampling the newly addressed analog input after the fourth falling edge of the I/O

CLOCK. The sampling operation basically involves charging the internal capacitors to the level of the analog

input voltage.

3.

Three clock cycles are applied to the I/O CLOCK terminal and the sixth, seventh, and eighth conversion

bits are shifted out on the negative edges of these clock cycles.

4.

The final eighth clock cycle is applied to the I/O CLOCK terminal. The falling edge of this clock cycle initiates

a 12-system clock (

≈ 12 µs) additional sampling period while the output is in the high-impedance state.

Conversion is then performed during the next 20

µs. After this final I/O CLOCK cycle, CS must go high or

the I/O CLOCK must remain low for at least 20

µs to allow for the conversion function.

CS can be kept low during periods of multiple conversion. If CS is taken high, it must remain high until the end of

conversion. Otherwise, a valid falling edge of CS causes a reset condition, which aborts the conversion process.

A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through

4 before the 20-

µs conversion time has elapsed. Such action yields the conversion result of the previous conversion

and not the ongoing conversion.

The end-of-conversion (EOC) output goes low on the negative edge of the eighth I/O CLOCK. The subsequent

low-to-high transition of EOC indicates the A/D conversion is complete and the conversion is ready for transfer.