TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT

TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT

DYNAMIC RAM MODULES

SMMS679 – MARCH 1997

1

POST OFFICE BOX 1443

TM124BBK32H / I...1048 576

× 32

TM248CBK32H / I...2097 152

× 32

(SIMM) for Use With Socket

DRAMs in Plastic Small-Outline J-Lead

(SOJ) Packages

DRAMs in Plastic SOJ Packages

16 ms (1 024 Cycles)

TTL-Compatible

Data-In and Data-Out Lines in Four Blocks

CAS-Before-RAS ( CBR ), RAS-Only, and

Hidden Refresh

ACCESS ACCESS ACCESS READ

TIME

TIME

TIME

OR

tRAC

tAA

tCAC

WRITE

CYCLE

(MAX)

(MAX)

(MAX)

(MIN)

’124BBK32H / I-50 50 ns

25 ns

13 ns

90 ns

’124BBK32H / I-60 60 ns

30 ns

15 ns

110 ns

’124BBK32H / I-70 70 ns

35 ns

18 ns

130 ns

’248CBK32H / I-50 50 ns

25 ns

13 ns

90 ns

’248CBK32H / I-60 60 ns

30 ns

15 ns

110 ns

’248CBK32H / I-70 70 ns

35 ns

18 ns

130 ns

0

°C to 70°C

TM124BBK32H

TM248CBK32H

Available:

TM124BBK32I

TM248CBK32I

description

TM124BBK32H / I

The TM124BBK32H / I is a 32M-bit dynamic random-access memory (DRAM) module organized as four times

1 048 576

× 8 in a 72-pin SIMM. The SIMM is composed of two TMS418160ADZ, 1 048 576 × 16-bit DRAMs,

each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The

TMS418160ADZ is described in the TMS418160A data sheet (literature number SMKS891). The

TM124BBK32H/ I SIMM is available in the single-sided BK-leadless module for use with sockets.

TM248CBK32H / I

The TM248CBK32H / I is a 64M-bit DRAM organized as four times 2 097 152

× 8 in a 72-pin SIMM. The SIMM

is composed of four TMS418160ADZ, 1 048 576

× 16-bit DRAMs, each in a 42-lead plastic SOJ package

mounted on a substrate with decoupling capacitors. The TMS418160ADZ is described in the TMS418160A data

sheet (literature number SMKS891). The TM248CBK32H / I SIMM is available in the double-sided BK-leadless

module for use with sockets.

operation

The TM124BBK32H / I operates as two TMS418160ADZ DRAMs, connected as shown in the functional block

diagram and Table 1. The TM248CBK32H / I operates as four TMS418160ADZ DRAMs connected as shown

in the functional block diagram and Table 1. The common I / O feature dictates the use of early-write cycles to

prevent contention on D and Q.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

† Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright

 1997, Texas Instruments Incorporated