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TM124MBK36U-60 Datasheet(PDF) 8 Page - Texas Instruments |
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TM124MBK36U-60 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 9 page TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) ’124MBK36F - 60 ’248NBK36F - 60 ’124MBK36F - 70 ’248NBK36F - 70 ’124MBK36F - 80 ’248NBK36F - 80 UNIT MIN MAX MIN MAX MIN MAX tCHR Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns tCRP Delay time, CAS high to RAS low 5 5 5 ns tCSH Delay time, RAS low to CAS high 60 70 80 ns tCSR Delay time, CAS low to RAS low (CBR refresh only) 5 5 5 ns tRAD Delay time, RAS low to column address (see Note 10) 15 30 15 35 15 40 ns tRAL Delay time, column address to RAS high 30 35 40 ns tCAL Delay time, column address to CAS high 30 35 40 ns tRCD Delay time, RAS low to CAS low (see Note 10) 20 45 20 52 20 60 ns tRPC Delay time, RAS high to CAS low (CBR only) 0 0 0 ns tRSH Delay time, CAS low to RAS high 15 18 20 ns tREF Refresh time interval 16 16 16 ms tT Transition time 3 30 3 30 3 30 ns NOTE 10: The maximum value is specified only to assure access time. device symbolization (TM124MBK36F illustrated) TM124MBK36F -SS YYMMT YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE: Location of symbolization may vary. |
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