TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT

TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT

DYNAMIC RANDOM-ACCESS MEMORY MODULES

SMMS653B – MAY 1995 – REVISED JULY 1995

2

POST OFFICE BOX 1443

operation

TM497MBM36A

The TM497MBM36A operates as eight TMS417400DJs and four TMS44100DJs connected as shown in the

functional block diagram and in Table 1. The common I / O feature dictates the use of early-write cycles to prevent

contention on D and Q.

TM893NBM36A

The TM893NBM36A operates as sixteen TMS417400DJs and eight TMS44100DJs connected as shown in the

functional block diagram and in Table 1. The common I / O feature dictates the use of early-write cycles to prevent

contention on D and Q.

refresh

The refresh period is extended to 32 ms, and, during this period, each of the 2 048 rows must be strobed with

RAS in order to retain data. Address line A10 must be used as the most significant refresh address line (lowest

frequency) to ensure correct refresh for both TMS417400 and TMS44100. Address lines A0 – A9 must be

refreshed every 16 ms as required by the TMS44100 DRAM. To conserve power, CAS can remain high during

the refresh sequence.

power up

To achieve proper operation, an initial pause of 200

µs followed by a minimum of eight initialization cycles is

(RAS-only or CBR-refresh) cycle.

Table 1. Connection Table

DATA BLOCK

RASx

CASx

DATA BLOCK

SIDE 1

SIDE 2 †

CASx

DQ0 – DQ7

DQ8

RAS0

RAS1

CAS0

DQ9 – DQ16

DQ17

RAS0

RAS1

CAS1

DQ18 – DQ25

DQ26

RAS2

RAS3

CAS2

DQ27 – DQ34

DQ35

RAS2

RAS3

CAS3

† Side 2 applies to the TM893NBM36A.

single in-line memory module and components

PC substrate: 1, 27

± 0,1 mm (0.05 inch) nominal thickness; inch/inch maximum warpage

Bypass capacitors: Multilayer ceramic

Contact area for TM497MBM36A and TM893NBM36A: Nickel plate and gold plate over copper

Contact area for TM497MBM36Q and TM893NBM36Q: Nickel plate and tin / lead over copper