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SN74LS224AN Datasheet(PDF) 7 Page - Texas Instruments |
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SN74LS224AN Datasheet(HTML) 7 Page - Texas Instruments |
7 / 13 page SN54LS224A, SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS SDLS023E – JANUARY 1991 – REVISED APRIL 2003 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating conditions (see Note 4 and Figure 1) SN54LS224A SN74LS224A UNIT MIN MAX MIN MAX UNIT LDCK high 60 60 LDCK low 15 15 tw Pulse duration UNCK low 30 30 ns UNCK high 30 30 CLR low 20 20 Data to LDCK ↓ 50 50 tsu Setup time LDCK ↓ before UNCK↓ 50 50 ns UNCK ↑ before LDCK↑ 50 50 th Hold time Data from LDCK ↓ 10 10 ns NOTE 4: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs. Any excessive noise or glitching on the clock inputs that violates the VIL, VIH, or minimum pulse-duration limits can cause a false clock or improper operation of the internal read and write pointers. switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPLH LDCK ↓ IR RL =2kΩ CL =15 pF 25 40 ns tPHL LDCK ↑ IR RL = 2 kΩ, CL = 15 pF 36 50 ns tPLH LDCK ↓ OR RL = 2 kΩ, CL = 15 pF 48 70 ns tPLH UNCK ↑ OR RL =2kΩ CL =15 pF 29 45 ns tPHL UNCK ↓ OR RL = 2 kΩ, CL = 15 pF 28 45 ns tPLH UNCK ↑ IR RL = 2 kΩ, CL = 15 pF 49 70 ns tPLH CLR ↓ IR RL =2kΩ CL =15 pF 36 55 ns tPHL CLR ↓ OR RL = 2 kΩ, CL = 15 pF 25 40 ns tPHL LDCK ↓ Q RL = 667 Ω, CL = 45 pF 34 50 ns tPLH UNCK ↑ Q RL = 667 Ω CL =45 pF 54 80 ns tPHL UNCK ↑ Q RL = 667 Ω, CL = 45 pF 45 70 ns tPZL OE ↑ Q RL = 667 Ω CL =45 pF 22 35 ns tPZH OE ↑ Q RL = 667 Ω, CL = 45 pF 21 35 ns tPLZ OE ↓ Q RL = 667 Ω CL =5 pF 16 30 ns tPHZ OE ↓ Q RL = 667 Ω, CL = 5 pF 18 30 ns |
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