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SN65HVD251QDRQ1 Datasheet(PDF) 5 Page - Texas Instruments |
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SN65HVD251QDRQ1 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 20 page  www.ti.com RECEIVER ELECTRICAL CHARACTERISTICS RECEIVER SWITCHING CHARACTERISTICS VREF PIN CHARACTERISTICS SN65HVD251-Q1 SLLS788 – APRIL 2007 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIT+ Positive-going input threshold voltage 750 900 VIT– Negative-going input threshold voltage Rs at 0 V, (See Table 1) 500 650 mV Vhys Hysteresis voltage (VIT+ – VIT–) 100 VOH High-level output voltage Figure 6, IO = –4 mA 0.8 VCC V VOL Low-level output voltage Figure 6, IO = 4 mA 0.2 VCC V CANH or CANL at 12 V 600 CANH or CANL at 12 V, 715 Other bus pin at VCC at 0 V II Bus input current 0 V, Rs at 0 V, A CANH or CANL at –7 V –460 D at 0.7 VCC CANH or CANL at –7 V, –340 VCC at 0 V Pin-to-ground, VI = 0.4 sin (4E6πt) + 0.5 V, pF CI Input capacitance (CANH or CANL) 20 D at 0.7 VCC Pin-to-pin, VI = 0.4 sin (4E6πt) + 0.5 V, pF CID Differential input capacitance 10 D at 0.7 VCC RID Differential input resistance D at 0.7 VCC, Rs at 0 V 40 100 k Ω RIN Input resistance (CANH or CANL) D at 0.7 VCC, Rs at 0 V 20 50 k Ω Standby Rs at VCC, D at VCC 275 A ICC Supply current Dominant D at 0 V, 60- Ω load, Rs at 0 V 65 mA Recessive D at VCC, No load, Rs at 0 V 14 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tpLH Propagation delay time, low-to-high-level output 35 50 ns tpHL Propagation delay time, high-to-low-level output 35 50 ns tsk(p) Pulse skew (|tpHL – tpLH|) Figure 6 20 ns tr Output signal rise time 2 4 ns tf Output signal fall time 2 4 ns tp(sb) Propagation delay time in standby Figure 12, Rs at VCC 500 ns over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT –5 μA < IO < 5 μA 0.45 VCC 0.55 VCC VO Reference output voltage V –50 μA < IO < 50 μA 0.4 VCC 0.6 VCC 5 Submit Documentation Feedback |
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