SN74ACT74EP

DUAL POSITIVEEDGETRIGGERED DTYPE FLIPFLOP

WITH CLEAR AND PRESET

SCAS722 − OCTOBER 2003

3

POST OFFICE BOX 655303

recommended operating conditions (see Note 4)

MIN

MAX

UNIT

VCC

Supply voltage

4.5

5.5

V

VIH

High-level input voltage

2

V

VIL

Low-level input voltage

0.8

V

VI

Input voltage

0

VCC

V

VO

Output voltage

0

VCC

V

IOH

High-level output current

−24

mA

IOL

Low-level output current

24

mA

∆t/∆v

Input transition rise or fall rate

8

ns/V

TA

Operating free-air temperature

−55

125

°C

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

TA = 25°C

MIN

MAX

UNIT

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

MIN

MAX

UNIT

IOH = −50 A

4.5 V

4.4

4.49

4.4

VOH

IOH = −50 µA

5.5 V

5.4

5.49

5.4

V

VOH

IOH = −24 mA

4.5 V

3.86

3.7

V

IOH = −24 mA

5.5 V

4.86

4.7

IOL = 50 A

4.5 V

0.001

0.1

0.1

VOL

IOL = 50 µA

5.5 V

0.001

0.1

0.1

V

VOL

IOL = 24 mA

4.5 V

0.36

0.5

V

IOL = 24 mA

5.5 V

0.36

0.5

II

VI = VCC or GND

5.5 V

±0.1

±1

µA

ICC

VI = VCC or GND,

IO = 0

5.5 V

2

40

µA

∆ICC†

One input at 3.4 V,

Other inputs at GND or VCC

5.5 V

0.6

1.6

mA

Ci

VI = VCC or GND

5 V

3

pF

† This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

timing characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 1)

TA = 25°C

MIN

MAX

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

145

85

MHz

tw

Pulse duration

PRE or CLR low

5

7

ns

tw

Pulse duration

CLK

5

7

ns

tsu

Setup time, data before CLK

↑

Data

3

4

ns

tsu

Setup time, data before CLK

↑

PRE or CLR inactive

0

0.5

ns

th

Hold time, data after CLK

↑

1

1

ns