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M74VHC1GT126DF2G Datasheet(PDF) 1 Page - ON Semiconductor

Part # M74VHC1GT126DF2G
Description  Noninverting Buffer / CMOS Logic Level Shifter with LSTTL.Compatible Inputs
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

M74VHC1GT126DF2G Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2012
May, 2012 − Rev. 15
1
Publication Order Number:
MC74VHC1GT126/D
MC74VHC1GT126
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHC1GT126 is a single gate noninverting 3−state buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHC1GT126 requires the 3−state control input (OE) to be
set Low to place the output into the high impedance state.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to
3 V CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT126 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT126 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V
CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 62; Equivalent Gates = 16
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
Figure 1. Pinout (Top View)
IN A
OUT Y
VCC
OE
IN A
OUT Y
GND
OE
Figure 2. Logic Symbol
1
2
3
4
5
PIN ASSIGNMENT
1
2
3
GND
OE
IN A
4
5VCC
OUT Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
FUNCTION TABLE
L
H
X
A Input
Y Output
L
H
Z
OE Input
H
H
L
http://onsemi.com
SC−88A / SOT−353 / SC−70
DF SUFFIX
CASE 419A
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
CASE 483
MARKING
DIAGRAMS
1
5
1
5
1
5
W3 M G
G
W3
= Device Code
M
= Date Code*
G
= Pb−Free Package
1
5
W3 M G
G
*Date Code orientation and/or position may vary
depending upon manufacturing location.
(Note: Microdot may be in either location)


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