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Z51F0410 Datasheet(PDF) 7 Page - Zilog, Inc.

Part # Z51F0410
Description  Z8051 Series 8-Bit Microcontrollers
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z51F0410 Datasheet(HTML) 7 Page - Zilog, Inc.

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Z51F0410
Product Specification
PS029502-0212
P R E L I M I N A R Y
4
4.9.2 Block Diagram................................................................................................................. 132
4.9.3 IN/OUT signal description ............................................................................................... 132
4.9.4 Register Map................................................................................................................... 133
4.9.5 Analog Comparator Register description......................................................................... 133
4.9.6 Register description for Analog Comparator ................................................................... 133
4.10 Buzzer Driver ....................................................................................................................... 134
4.10.1 Overview....................................................................................................................... 134
4.10.2 Block Diagram............................................................................................................... 135
4.10.3 Register Map................................................................................................................. 135
4.10.4 Buzzer Driver Register description................................................................................ 135
4.10.5 Register description for Buzzer Driver........................................................................... 135
5. Power Down Operation ................................................................................................................ 137
5.1 Overview ................................................................................................................................ 137
5.2 Peripheral Operation In IDLE/STOP Mode............................................................................. 137
5.3 IDLE mode ............................................................................................................................. 137
5.4 STOP mode ........................................................................................................................... 139
5.5 Release Operation of STOP1, 2 Mode ................................................................................... 140
5.5.1 Register Map................................................................................................................... 140
5.5.2 Power Down Operation Register description................................................................... 141
5.5.3 Register description for Power Down Operation.............................................................. 141
6. RESET ......................................................................................................................................... 142
6.1 Overview ................................................................................................................................ 142
6.2 Reset source .......................................................................................................................... 142
6.3 Block Diagram........................................................................................................................ 142
6.4 RESET Noise Canceller ......................................................................................................... 142
6.5 Power ON RESET.................................................................................................................. 143
6.6 External RESETB Input.......................................................................................................... 145
6.7 Brown Out Detector Processor............................................................................................... 146
6.7.1 Register Map................................................................................................................... 148
6.7.2 Reset Operation Register description ............................................................................. 148
6.7.3 Register description for Reset Operation ........................................................................ 148
7. On-chip Debug System ................................................................................................................ 150
7.1 Overview ................................................................................................................................ 150
7.1.1 Description ...................................................................................................................... 150
7.1.2 Feature ........................................................................................................................... 150
7.2 Two-pin external interface ...................................................................................................... 151
7.2.1 Basic transmission packet............................................................................................... 151
7.2.2 Packet transmission timing ............................................................................................. 152
7.2.3 Connection of transmission............................................................................................. 153
8. Memory Programming .................................................................................................................. 155
8.1 Overview ................................................................................................................................ 155
8.1.1 Description ...................................................................................................................... 155
8.1.2 Features.......................................................................................................................... 155
8.2 Flash and EEPROM Control and status register .................................................................... 155
8.2.1 Register Map................................................................................................................... 155
8.2.2 Register description for Flash and EEPROM .................................................................. 156
8.3 Memory map .......................................................................................................................... 160
8.3.1 Flash Memory Map ......................................................................................................... 160


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