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BL35P02 DATASHEET

BL35P02 DATASHEET

BL35P02 DATASHEET

BL35P02 DATASHEET

上海贝岭股份

上海贝岭股份

上海贝岭股份

上海贝岭股份有限公司

有限公司

有限公司

有限公司

Shanghai Belling Co., Ltd.

MCR

$0C

R/W

00-0 0000

Notice：

-: is undefined；

u: is unaffected.

PA

PA

PA

PA ($00): P

($00): P

($00): P

($00): Port A Data Register

ort A Data Register

ort A Data Register

ort A Data Registers

ss

s

.7-.0 PA[7:0]

When a Port A pin is programmed as an output the state of the corresponding data register bit

determines the state of the output pin.

When a Port A pin is programmed as an input, a read of the Port A Data Register will return the

logic state of the corresponding Port A pin.

DDRA($0

DDRA($0

DDRA($0

DDRA($04

44

4): Port A Data Direction Registers

): Port A Data Direction Registers

): Port A Data Direction Registers

): Port A Data Direction Registers

.7-.0 DDRA[7:0]

Port A pin may be programmed as an input or output by clearing or setting the corresponding bit

int DDRA.

0 (clear) - Port A pin is used as an input

1 (set)

- Port A pin is used as output

PB ($02): P

PB ($02): P

PB ($02): P

PB ($02): Port B Data Registers

ort B Data Registers

ort B Data Registers

ort B Data Registers

.7-.2,.0 PB[7:2,0]

When a Port B pin is programmed as an output the state of the corresponding data register bit

determines the state of the output pin.

When a Port B pin is programmed as an input, a read of the Port B Data Register will return the

logic state of the corresponding Port B pin.

DDRB($0

DDRB($0

DDRB($0

DDRB($05

55

5):

):

):

): Port B Data Direction Registers

Port B Data Direction Registers

Port B Data Direction Registers

Port B Data Direction Registers

.7-.2 DDRB[7:2]

Port B pin may be programmed as an input or output by clearing or setting the corresponding bit

int DDRA.

0 (clear) - Port A pin is used as an input

1 (set)

- Port A pin is used as output

.0 KBEB0 – PB0 Keyboard Interrupt Enable

KBEB0 is a keyboard Interrupt Enable bit of PB0 pin。

0 (clear) – Keyboard interrupt of PB0 pin disabled.

1 (set)

- Keyboard interrupt of PB0 pin enabled. PB0 has no pull-up resistor.

TDR($08):

TDR($08):

TDR($08):

TDR($08): Timer Data Register

Timer Data Register

Timer Data Register

Timer Data Register

The TDR is a read/write register which contains the current value of the 8-bit count-down timer

counter when read. Reading this register does not disturb the counter operation.

TCR($09):

TCR($09):

TCR($09):

TCR($09): Timer Control Register

Timer Control Register

Timer Control Register

Timer Control Register

.7 TIF – Timer Interrupt Flag

0 (clear) – The timer has not reached a count of zero.

1 (set)

- The timer has reached a count of zero.

The timer interrupt flag is set when the 8-bit counter decrements to zero. This bit is cleared on

reset, or by writing a “0” to the TIF bit.

.6 TIM – Timer Interrupt Mask

0 (clear) – Timer interrupt request to the CPU is not masked (enable).

1 (set) – Timer interrupt request to the CUP is masked (disable).