Integrated Silicon Solution, Inc.

1

Rev. L

09/06/12

Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,

IS61VPS51218A, IS61VPS25636A

FEATURES

• Internalself-timedwritecycle

• IndividualByteWriteControlandGlobalWrite

• Clockcontrolled,registeredaddress,dataand

control

• BurstsequencecontrolusingMODEinput

• Threechipenableoptionforsimpledepthex-

pansion and address pipelining

• Commondatainputsanddataoutputs

• AutoPower-downduringdeselect

• Singlecycledeselect

• SnoozeMODEforreduced-powerstandby

• JTAGBoundaryScanforPBGApackage

• PowerSupply

• JEDEC100-PinTQFP,119-ballPBGA,and

165-ballPBGApackages

• Lead-freeavailable

DESCRIPTION

The

IS64LPS25636A and IS61LPS/VPS51218A are high-

speed, low-power synchronous static RAMs designed

to provide burstable, high-performance memory for com-

municationandnetworkingapplications.TheIS61LPS/

VPS25636A and IS64LPS25636A are organized as

262,144 words by 36 bits.The IS61LPS25632A is

organizedas262,144wordsby32bits.TheIS61LPS/

VPS51218Aisorganizedas524,288wordsby18bits.

Fabricated with

thedeviceintegratesa2-bitburstcounter,high-speed

SRAMcore,andhigh-drivecapabilityoutputsintoasingle

monolithic circuit. All synchronous inputs pass through

registerscontrolledbyapositive-edge-triggeredsingle

clock input.

Writecyclesareinternallyself-timedandareinitiatedby

therisingedgeoftheclockinput.Writecyclescanbe

one to four bytes wide as controlled by the write control

inputs.

Separate byte enables allow individual bytes to be written.

Thebytewriteoperationisperformedbyusingthebyte

write enable (BWE) input combined with one or more

individual byte write signals (BWx). Inaddition,Global

Write(GW) is available for writing all bytes at one time,

regardless of the byte write controls.

BurstscanbeinitiatedwitheitherADSP (Address Status

Processor)orADSC (Address Status Cache Controller)

inputpins.Subsequentburstaddressescanbegener-

ated internally and controlled by the ADV (burst address

advance) input pin.

Themodepinisusedtoselecttheburstsequenceor-

der,LinearburstisachievedwhenthispinistiedLOW.

InterleaveburstisachievedwhenthispinistiedHIGH

or left floating.

256K x 36, 256K x 32, 512K x 18

9 Mb SYNCHRONOUS PIPELINED,

SINGLE CYCLE DESELECT STATIC RAM

SEPTEMBER 2012

FAST ACCESS TIME

Symbol

Parameter

250

200

166

Units

ClockAccessTime

2.6

3.1

3.5

ns

CycleTime

4

5

6

ns

Frequency

250

200

166

MHz