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IS66WVE2M16DALL

Rev. B | May 2012

www.issi.com - SRAM@issi.com

Partial-Array Refresh

Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory

array. This feature enables the device to reduce standby current by refreshing only that

part of the memory array that is absolutely necessary. The refresh options are full array,

and none of the array. Data stored in addresses not receiving refresh will become

corrupted. Read and WRITE operations are ignored during PAR operation.

The device only enters PAR mode if the sleep bit in the CR has been set HIGH (CR[4] = 1).

PAR can be initiated by taking the ZZ# ball to the LOW state for longer than 10us.

Returning ZZ# to HIGH will cause an exit from PAR, and the entire array will be immediately

available for READ and WRITE operations.

Alternatively, PAR can be initiated using the CR software-access sequence (see “Software

Access to the Configuration Register”). Using this method, PAR is enabled

immediately upon setting CR[4] to “1” However, using software access to write to the CR

alters the function of ZZ# so that ZZ# LOW no longer initiates PAR, even though ZZ#

continues to enable WRITEs to the CR. This functional change persists until the next

time the device is powered up.

Deep Power-Down Operation

Deep power-down (DPD) operation disables all refresh-related activity. This mode is

used if the system does not require the storage provided by the PSRAM device. Any

stored data will become corrupted upon entering DPD. When refresh activity has been

re-enabled, the PSRAM device will require 150μs to perform an initialization procedure

before normal operations can resume. READ and WRITE operations are ignored during

DPD operation.

The device can only enter DPD if the sleep bit in the CR has been set LOW (CR[4] =0).

DPD is initiated by bringing ZZ# to the LOW state for longer than 10us. Returning ZZ# to

HIGH will cause the device to exit DPD and begin a 150us initialization process. During

this time, the current consumption will be higher than the specified standby levels, but

considerably lower than the active current specification.

Driving ZZ# LOW puts the device in PAR mode if the SLEEP bit in the CR has been set

HIGH (CR[4] = 1).

The device should not be put into DPD using the CR software-access sequence.