6

IS66WVE2M16DBLL

Rev.A | May 2012

www.issi.com - SRAM@issi.com

Functional Description

In general, this device is high-density alternatives to SRAM and Pseudo SRAM products popular

in low-power, portable applications.

The 32Mb device contains a 33,554,432-bit DRAM core organized as 2,097,152 addresses by

16 bits. This device include the industry-standard, asynchronous memory interface found on

other low-power SRAM or PSRAM offerings

Page mode access is also supported as a bandwidth-enhancing extension to the asynchronous

read protocol.

Power-Up Initialization

PSRAM products include an on-chip voltage sensor that is used to launch the power-up

initialization process. Initialization will load the CR with its default settings (see Table 3).

VDD and VDDQ must be applied simultaneously. When they reach a stable level above

2.7V, the device will require 150μs to complete its self-initialization process ( see Figure 1).

During the initialization period, CE# should remain HIGH. When initialization is complete,

the device is ready for normal operation.

Figure 1: Power-Up Initialization Timing

VDD=2.7V

Device Initialization

tPU > 150us

Device ready for

normal operation

VDD

VDDQ