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IS25LD512 Datasheet(PDF) 7 Page - Integrated Silicon Solution, Inc |
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IS25LD512 Datasheet(HTML) 7 Page - Integrated Silicon Solution, Inc |
7 / 43 page IS25LD512/010/020 Integrated Silicon Solution, Inc.- www.issi.com Rev. A 08/09/2012 7 REGISTERS (CONTINUED) Table 6. Status Register Bit Definition Bit Name Definition Read- /Write Non-Volatile bit Bit 0 WIP Write In Progress Bit: "0" indicates the device is ready "1" indicates a write cycle is in progress and the device is busy R No Bit 1 WEL Write Enable Latch: "0" indicates the device is not write enabled "1" indicates the device is write enabled (default) R/W No Bit 2 BP0 Block Protection Bit: (See Table 7 and Table 8 for details) "0" indicates the specific blocks are not write-protected (default) "1" indicates the specific blocks are write-protected R/W Yes Bit 3 BP1 Bit 4 BP2 Bits 5 - 6 N/A Reserved: Always "0"s N/A Bit 7 SRWD Status Register Write Disable: (See Table 9 for details) "0" indicates the Status Register is not write-protected (default) "1" indicates the Status Register is write-protected R/W Yes Table 8. Block Write Protect Bits for IS25LD512/010/020 Status Register Bits Protected Memory Area BP1 BP0 IS25LD512A IS25LD010A IS25LD020 0 0 None None None 0 1 None Upper quarter (Block 3) 01800h-01FFFFh Upper quarter (Block 3) 03000h-03FFFFh 1 0 None Upper half (Block 2 & 3) 010000h-01FFFFh Upper half (Block 2 & 3) 020000h-03FFFFh 1 1 All Blocks 000000h-00FFFFh All Blocks 000000h-01FFFFh All Blocks 000000h-03FFFFh |
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