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IS49NLC36800 Datasheet(PDF) 7 Page - Integrated Silicon Solution, Inc |
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IS49NLC36800 Datasheet(HTML) 7 Page - Integrated Silicon Solution, Inc |
7 / 34 page IS49NLC93200,IS49NLC18160,IS49NLC36800 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00F, 06/20/2012 7 2.4 Operating Conditions and Maximum Limits Description Condition Symbol -18 -25E -25 -33 -5 units Standby current tCK = idle; All banks idle; No inputs toggling ISB1(VDD) x9/x18 55 53 48 48 48 mA ISB1(VDD) x36 55 53 48 48 48 ISB1(VEXT) 5 5 5 5 5 Active standby current CS# =1; No commands; Bank address incremented and half address/data change once every 4 clock cycles ISB2(VDD) x9/x18 365 293 288 233 189 mA ISB2(VDD) x36 365 293 288 233 189 ISB2(VEXT) 5 5 5 5 5 Operational current BL=2; Sequential bank access; Bank transitions once every tRC; Half address transitions once every tRC; Read followed by write sequence; continuous data during WRITE commands IDD1(VDD) x9/x18 465 380 348 305 255 mA IDD1(VDD) x36 485 400 374 343 292 IDD1(VEXT) 15 15 15 13 13 BL = 4; Sequential bank access; Bank transitions once every tRC; Half address transitions once every tRC; Read followed by write sequence; Continuous data during WRITE commands IDD2(VDD) x9/x18 475 400 362 319 269 mA IDD2(VDD) x36 510 425 418 389 339 IDD2(VEXT) 15 15 15 13 13 BL = 8; Sequential bank access; Bank transitions once every tRC; half address transitions once every tRC; Read followed by write sequence; continuous data during WRITE commands IDD3 (VDD) x9/x18 505 430 408 368 286 mA IDD3 (VDD) x36 625 540 460 425 425 IDD3(VEXT) 20 20 20 18 18 Burst refresh current Eight-bank cyclic refresh; Continuous address/data; Command bus remains in refresh for all eight banks IREF1(VDD) x9/x18 995 790 785 615 430 mA IREF1(VDD) x36 995 915 785 615 430 IREF1(VEXT) 80 80 80 70 70 Distributed refresh current Single-bank refresh; Sequential bank access; Half address transitions once every tRC, continuous data IREF2(VDD) x9/x18 425 330 325 267 221 mA IREF2(VDD) x36 425 390 326 281 227 IREF2(VEXT) 20 20 20 18 18 Operating burst write current BL=2; Cyclic bank access; Half of address bits change every clock cycle; Continuous data; measurement is taken during continuous WRITE IDD2W(VDD) x9/x18 1335 980 970 819 597 mA IDD2W(VDD) x36 1545 1105 990 914 676 IDD2W(VEXT) 50 50 50 40 40 BL=4; Cyclic bank access; Half of address bits change every 2 clock cycles; Continuous data; Measurement is taken during continuous WRITE IDD4W(VDD) x9/x18 985 785 779 609 439 mA IDD4W(VDD) x36 1185 887 882 790 567 IDD4W(VEXT) 30 30 30 25 25 BL=8; Cyclic bank access; Half of address bits change every 4 clock cycles; continuous data; Measurement is taken during continuous WRITE IDD8W(VDD) x9/x18 770 675 668 525 364 mA IDD8W(VDD) x36 1095 755 750 580 580 IDD8W(VEXT) 30 30 30 25 25 Operating burst read current BL=2; Cyclic bank access; Half of address bits change every clock cycle; Measurement is taken during continuous READ IDD2R(VDD) x9/x18 1225 940 935 735 525 mA IDD2R(VDD) x36 1270 995 990 795 565 IDD2R(VEXT) 50 50 50 40 40 BL=4; Cyclic bank access; Half of address bits change every clock cycle; Measurement is taken during continuous READ IDD4R(VDD) x9/x18 860 685 680 525 380 mA IDD4R(VDD) x36 920 735 730 660 455 IDD4R(VEXT) 30 30 30 25 25 BL=8; Cyclic bank access; Half of address bits change every clock cycle; Measurement is taken during continuous READ IDD8R(VDD) x9/x18 655 575 570 450 310 mA IDD8R(VDD) x36 855 665 660 505 505 IDD8R(VEXT) 30 30 30 25 25 |
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