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IS49NLS93200 Datasheet(PDF) 5 Page - Integrated Silicon Solution, Inc

Part # IS49NLS93200
Description  288Mb (x9, x18) Separate I/O RLDRAM 2 Memory
Download  34 Pages
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS49NLS93200 Datasheet(HTML) 5 Page - Integrated Silicon Solution, Inc

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IS49NLS93200,IS49NLS18160
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00F, 09/25/2012
5
2 Electrical Specifications
2.1 Absolute Maximum Ratings
Item
Min
Max
Units
I/O Voltage
0.3
VDDQ + 0.3
V
Voltage on VEXT supply relative to VSS
0.3
2.8
V
Voltage on VDD supply relative to VSS
0.3
2.1
V
Voltage on VDDQ supply relative to VSS
0.3
2.1
V
Note: Stress greater than those listed in this table may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2.2 DC Electrical Characteristics and Operating Conditions
Description
Conditions
Symbol
Min
Max
Units
Notes
Supply voltage
VEXT
2.38
2.63
V
Supply voltage
VDD
1.7
1.9
V
2
Isolated output buffer supply
VDDQ
1.4
VDD
V
2,3
Reference voltage
VREF
0.49 x VDDQ
0.51 x VDDQ
V
4,5,6
Termination voltage
VTT
0.95 x VREF
1.05 x VREF
V
7,8
Input high voltage
VIH
VREF + 0.1
VDDQ + 0.3
V
2
Input low voltage
VIL
VSSQ − 0.3
VREF − 0.1
V
2
Output high current
VOH = VDDQ/2
IOH
(VDDQ/2)/
(VDDQ/2)/
A
9, 10,
11
(1.15 x RQ/5)
(0.85 x RQ/5)
Output low current
VOL = VDDQ/2
IOL
(VDDQ/2)/
(VDDQ/2)/
A
9, 10,
11
(1.15 x RQ/5)
(0.85 x RQ/5)
Clock input leakage current
0V ≤ VIN ≤ VDD
ILC
− 5
5
µA
Input leakage current
0V ≤ VIN ≤ VDD
ILI
− 5
5
µA
Output leakage current
0V ≤ VIN ≤ VDDQ
ILO
− 5
5
µA
Reference voltage current
IREF
− 5
5
µA
Notes:
1.
All voltages referenced to VSS (GND).
2.
Overshoot: VIH (AC) ≤ VDD + 0.7V for t ≤ tCK/2. Undershoot: VIL (AC) ≥ –0.5V for t ≤ tCK/2. During normal operation, VDDQ must not exceed VDD. Control input signals
may not have pulse widths less than tCK/2 or operate at frequencies exceeding tCK (MAX).
3.
VDDQ can be set to a nominal 1.5V ± 0.1V or 1.8V ± 0.1V supply.
4.
Typically the value of VREF is expected to be 0.5 x VDDQ of the transmitting device. VREF is expected to track variations in VDDQ.
5.
Peak-to-peak AC noise on VREF must not exceed ±2 percent VREF (DC).
6.
VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF
may not exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±2 percent VDDQ/2 for DC error and an additional ±2 percent VDDQ/2 for AC noise.
This measurement is to be taken at the nearest VREF bypass capacitor.
7.
VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
8.
On-die termination may be selected using mode register A9 (for non-multiplexed address mode) or Ax9 (for multiplexed address mode). A resistance RTT from
each data input signal to the nearest VTT can be enabled. RTT = 125–185Ω at 95°C TC.
9.
IOH and IOL are defined as absolute values and are measured at VDDQ /2. IOH flows from the device, IOL flows into the device.
10. If MRS bit A8 or Ax8 is 0, use RQ = 250Ω in the equation in lieu of presence of an external impedance matched resistor.
2.3 Capacitance
(TA = 25 °C, f = 1MHz)
Parameter
Symbol
Test Conditions
Min
Max
Units
Address / Control Input capacitance
CIN
VIN=0V
1.5
2.5
pF
I/O, Output, Other capacitance (D, Q, DM, QK, QVLD)
CIO
VIO=0V
3.5
5
pF
Clock Input capacitance
CCLK
VCLK=0V
2
3
pF
JTAG pins
CJ
VJ=0V
2
5
pF
Note. These parameters are not 100% tested and capacitance is not tested on ZQ pin.


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