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Integrated Silicon Solution, Inc. - www.issi.com

Rev. A

04/08/2011

IS42VM81600E / IS42VM16800E / IS42VM32400E

IS45VM81600E / IS45VM16800E / IS45VM32400E

Mobile SDRAM Functionality

ISSI’s128MbMobileSDRAMsarepincompatibleandhavesimilarfunctionalitywithISSI’sstandardSDRAMs,but

offerloweroperatingvoltagesandpowersavingfeatures.Fordetaileddescriptionsofpinfunctions,commandtruth

tables,functionaltruthtables,deviceoperationaswellastimingdiagramspleaserefertoISSIdocument“Mobile

SynchronousDRAMDeviceOperations&TimingDiagrams”listedatwww.issi.com

REGISTER DEFINITION

Mode Register (MR) & Extended Mode Register (EMR)

TherearetwomoderegistersintheMobileSDRAM;ModeRegister(MR)andExtendedModeRegister(EMR).The

ModeRegisterisdiscussedbelow,followedbytheExtendedModeRegister.TheModeRegisterisusedtodefine

thespecificmodeofoperationoftheSDRAM.Thisdefinitionincludestheselectionofburstlength,abursttype,CAS

Latency,operatingmode,andawriteburstmode.ThemoderegisterisprogrammedviatheLOADMODEREGISTER

commandandwillretainthestoredinformationuntilitisprogrammedagainorthedevicelosespower.

TheEMRcontrolsthefunctionsbeyondthosecontrolledbytheMR.Theseadditionalfunctionsarespecialfeatures

oftheMobileSDRAM.Theyincludetemperature-compensatedselfrefresh(TCSR)control,partial-arrayselfrefresh

(PASR),andoutputdrivestrength.TheEMRisprogrammedviatheMODEREGISTERSETcommandwithBA1

=1andBA0=0andretainsthestoredinformationuntilitisprogrammedagainorthedevicelosespower.Not

programmingtheextendedmoderegisteruponinitializationwillresultindefaultsettingsforthelow-powerfeatures.

Theextendedmodewilldefaultwiththetemperaturesensorenabled,fulldrivestrength,andfullarray(all4banks)

refresh.

Mode Register Definition

TheMRisusedtodefinethespecificmodeofoperationoftheSDRAM.Thisdefinitionincludestheselectionofa

burstlength,abursttype,aCASlatency,anoperatingmodeandawriteburstmode,asshowninFigureMODE

REGISTERDEFINITION.ThemoderegisterisprogrammedviatheLOADMODEREGISTERcommandandwill

retainthestoredinformationuntilitisprogrammedagainorthedevicelosespower.

ModeregisterbitsM0-M2specifytheburstlength,M3specifiesthetypeofburst(sequentialorinterleaved),M4-

M6specifytheCASlatency,M7andM8specifytheoperatingmode,M9specifiestheWRITEburstmode,andM10,

M11,andM12arereservedforfutureuse.

Themoderegistermustbeloadedwhenallbanksareidle,andthecontrollermustwaitthespecifiedtimebefore

initiatingthesubsequentoperation.Violatingeitheroftheserequirementswillresultinunspecifiedoperation.