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STA381BWS Datasheet(PDF) 9 Page - STMicroelectronics |
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STA381BWS Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 171 page STA381BWS Contents Doc ID 018937 Rev 6 9/171 7.16.3 Extended attack rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.16.4 Extended BIQUAD selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.17 EQ soft volume configuration registers (addr 0x37 - 0x38) . . . . . . . . . . 145 7.18 Extra volume resolution configuration registers (address 0x3F; 0x40) . . 146 7.19 PLL configuration registers (address 0x41; 0x42; 0x43; 0x44; 0x45; 0X46) . . . . . . . . . . . . . . . . . . . 147 7.20 Short-circuit protection mode registers SHOK (address 0x47) . . . . . . . 149 7.21 Extended coefficient range up to -4...4 (address 0x49, 0x4A) . . . . . . . . 151 7.22 Miscellaneous registers (address 0x4B, 0x4C) . . . . . . . . . . . . . . . . . . . 151 7.22.1 Rate power-down enable (RPDNEN) bit (address 0x4B, bit D7) . . . . . 151 7.22.2 Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5) . . . . . 152 7.22.3 Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2) . . . . . . . 152 7.22.4 External amplifier hardware pin enabler (LPDP, LPD LPDE) bits (address 0x4C, bit D7, D6, D5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 7.22.5 Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C, bit D4, D3, D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 7.22.6 Short-circuit check enable bit (address 0x4C, bit D0) . . . . . . . . . . . . . 153 7.23 Bad PWM detection registers (address 0x4D, 0x4E, 0x4F) . . . . . . . . . . 154 7.24 Enhanced zero-detect mute and input level measurement (address 0x50-0x54, 0x2E, 0x2F and 0x5E) . . . . . . . . . . . . . . . . . . . . . 155 7.25 Headphone/Line out configuration register (address 0x55) . . . . . . . . . . 157 7.26 F3XCFG (address 0x58; 0x59) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 7.27 STCompressorTM configuration register (address 0x5A; 0x5B) . . . . . . 159 7.28 Charge pump synchronization (address 0x5F) . . . . . . . . . . . . . . . . . . . 160 7.29 Coefficient RAM CRC protection (address 0x60-0x6C) . . . . . . . . . . . . . 161 7.30 MISC3 (address 0x6E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.31 MISC4 (address 0x7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8.1 Application schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8.2 Headphone and 2 Vrms line out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 8.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 |
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