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ST10F272M Datasheet(PDF) 21 Page - STMicroelectronics |
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ST10F272M Datasheet(HTML) 21 Page - STMicroelectronics |
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21 / 176 page  ST10F272M Memory organization Doc ID 12968 Rev 3 21/176 4 Memory organization The memory space of the ST10F272M is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16 Mbytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. IFlash: 256 Kbytes of on-chip Flash memory. It is divided in eight blocks (B0F0...B0F7) that constitute the bank 0. When bootstrap mode is selected, the test-Flash block B0TF (4 Kbytes) appears at address 00’0000h: refer to Section 5: Internal Flash memory for more details on memory mapping in boot mode. The summary of address range for IFlash is the following: IRAM: 2 Kbytes of on-chip internal RAM (dual-port) is provided as a storage for data, system stack, general purpose register banks and code. A register bank is 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) general purpose registers group. XRAM: 16K + 2K bytes of on-chip extension RAM (single port XRAM) is provided as a storage for data, user stack and code. The XRAM is divided into two areas, the first 2 Kbytes named XRAM1 and the second 16 Kbytes named XRAM2, connected to the internal XBUS and are accessed like an external memory in 16-bit demultiplexed bus-mode without wait state or read/write delay (50 ns access at 40 MHz CPU clock). Byte and word accesses are possible. The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register), and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is cleared, then any access in the address range 00’E000h - 00’E7FFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. The XRAM2 address range is the one selected programming XADRS3 register, if XPEN (bit 2 of SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is cleared, then any access in the address range programmed for XRAM2 will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. Table 2. Summary of IFlash address range Blocks User mode Size (bytes) B0TF Not visible 4K B0F0 00’0000h - 00’1FFFh 8K B0F1 00’2000h - 00’3FFFh 8K B0F2 00’4000h - 00’5FFFh 8K B0F3 00’6000h - 00’7FFFh 8K B0F4 01’8000h - 01’FFFFh 32K B0F5 02’0000h - 02’FFFFh 64K B0F6 03’0000h - 03’FFFFh 64K B0F7 04’0000h - 04’FFFFh 64K |
Similar Part No. - ST10F272M_12 |
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Similar Description - ST10F272M_12 |
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