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ST10F280 Datasheet(PDF) 53 Page - STMicroelectronics

Part # ST10F280
Description  16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F280 Datasheet(HTML) 53 Page - STMicroelectronics

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ST10F280
Central Processing Unit (CPU)
Doc ID 8673 Rev. 3
53/239
The system configuration register SYSCON
This bit-addressable register provides general system configuration and control functions.
The reset value for register SYSCON depends on the state of the PORT0 pins during reset.
SYSCON
Address:
0xFF12h / 89h SFR
Reset:
0x0XX0h
Type:
R/W
1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STKSZ
XPEN
R/W
R/W
R/W
R/W(1)
1.
These bit are set directly or indirectly according to PORT0 and EA pin configuration during reset sequence.
Register SYSCON cannot be changed after execution of the EINIT instruction.
R/W(1)
R/W
R/W(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XPEN XBUS Peripheral Enable Bit
0: Accesses to the on-chip X-Peripherals and their functions are disabled
1: The on-chip X-Peripherals are enabled and can be accessed.
BDRSTEN Bidirectional Reset Enable
0: RSTIN pin is an input pin only. SW Reset or WDT Reset have no effect on this pin
1: RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset
sequence.
OWDDIS Oscillator Watchdog Disable Control
0: Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors
XTAL1 activity. If there is no activity on XTAL1 for at least 1
μs, the CPU clock is
switched automatically to PLL’s base frequency (2 to 10MHz).
1: OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1
signal. The PLL is turned off to reduce power supply current.
PWDCFG Power Down Mode Configuration Control
0: Power Down Mode can only be entered during PWRDN instruction execution if NMI
pin is low, otherwise the instruction has no effect. To exit Power Down Mode, an
external reset must occurs by asserting the RSTIN pin.
1: Power Down Mode can only be entered during PWRDN instruction execution if all
enabled fast external interrupt EXxIN pins are in their inactive level. Exiting this mode
can be done by asserting one enabled EXxIN pin.
CSCFG Chip Select Configuration Control
0: Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE
1: Unlatched Chip Slect lines: CSx change with rising edge of ALE


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