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ST10F280 Datasheet(PDF) 57 Page - STMicroelectronics

Part # ST10F280
Description  16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F280 Datasheet(HTML) 57 Page - STMicroelectronics

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ST10F280
Central Processing Unit (CPU)
Doc ID 8673 Rev. 3
57/239
6.3
MAC coprocessor specific instructions
The following table gives an overview of the MAC instruction set. All the mnemonics are
listed with the addressing modes that can be used with each instruction.
For each combination of mnemonic and addressing mode this table indicates if it is
repeatable or not
New addressing capabilities enable the CPU to supply the MAC with up to 2 operands per
instruction cycle. MAC instructions: multiply, multiply-accumulate, 32-bit signed arithmetic
operations and the CoMOV transfer instruction have been added to the standard instruction
set. Full details are provided in the ‘ST10 Family Programming Manual’. Double indirect
addressing requires two pointers. Any GPR can be used for one pointer, the other pointer is
provided by one of two specific SFRs IDX0 and IDX1. Two pairs of offset registers QR0/QR1
and QX0/QX1 are associated with each pointer (GPR or IDXi).
The GPR pointer allows access to the entire memory space, but IDXi are limited to the
internal Dual-Port RAM, except for the CoMOV instruction.
RETS
Return from inter-segment subroutine
2
RETP
Return from intra-segment subroutine and pop direct
word register from system stack
2
RETI
Return from interrupt service subroutine
2
SRST
Software Reset
4
IDLE
Enter Idle Mode
4
PWRDN
Enter Power Down Mode (supposes NMI-pin being low)
4
SRVWDT
Service Watchdog Timer
4
DISWDT
Disable Watchdog Timer
4
EINIT
Signify End-of-Initialization on RSTOUT-pin
4
ATOMIC
Begin ATOMIC sequence
2
EXTR
Begin EXTended Register sequence
2
EXTP(R)
Begin EXTended Page (and Register) sequence
2 / 4
EXTS(R)
Begin EXTended Segment (and Register) sequence
2 / 4
NOP
Null operation
2
Table 4.
Instruction set summary (continued)
Mnemonic
Description
Bytes


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