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ST10F280 Datasheet(PDF) 5 Page - STMicroelectronics

Part # ST10F280
Description  16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F280 Datasheet(HTML) 5 Page - STMicroelectronics

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ST10F280
Contents
Doc ID 8673 Rev. 3
5/239
13.3.3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
14
Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
14.1
Asynchronous / Synchronous Serial Interface (ASCO) . . . . . . . . . . . . . 148
14.1.1
ASCO in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14.1.2
ASCO in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14.2
High speed synchronous serial channel (SSC) . . . . . . . . . . . . . . . . . . . 152
14.2.1
Baud rate generation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
15
CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
15.1
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
15.1.1
CAN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
15.1.2
CAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
15.2
CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
15.2.1
Single CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15.2.2
Multiple CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15.3
Register and message object organization . . . . . . . . . . . . . . . . . . . . . . 157
15.4
CAN interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
15.4.1
Bit timing configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
15.4.2
Mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
15.5
The message object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
15.6
Arbitration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
16
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
17
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
17.1
Asynchronous reset (long hardware reset) . . . . . . . . . . . . . . . . . . . . . . 171
17.1.1
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
17.1.2
Hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
17.1.3
Exit of asynchronous reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
17.2
Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
17.2.1
Exit of synchronous reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
17.3
Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
17.4
Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
17.5
RSTOUT pin and bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
17.6
Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175


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