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EMIF06-SD03F3 Datasheet(PDF) 7 Page - STMicroelectronics |
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EMIF06-SD03F3 Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 23 page EMIF06-SD03F3 Characteristics Doc ID 15194 Rev 2 7/23 Table 4. Recommended operating conditions Symbol Parameter Conditions Min. Typ. Max. Unit VccA Power supply 1.62 1.8 1.92 V Vbat Battery power supply 3.1 - 5 V Iout VccB output current 0.10 100 200 mA Cbat External battery capacitance Ceramic capacitor - 2.20 - µF Cout (1) External output capacitance Ta = -40 °C to +85 °C, Vbias = 0 V to 3.3 V Multi-layer ceramic capacitor type like: C20RX7R1C225K 1.4 (-35%) 2.20 3.0 (+35%) µF ESR(2) Equivalent series resistance for Cout F = 1 Hz to 10 MHz Multi-layer ceramic capacitor type like: C2012X7R1C225KT -3 200 m Ω Taop Ambient operating temperature -30 25 85 °C Tjop Juntion operating temperature -30 25 125 °C Pdop Maximum power dissipation Pdop = (Tjop - Taop)/Rth (j-a) -- 625 mW Enable Enable input voltage 0 - VccA V External pins (without WP and CD) CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B, Dat3-B 0 - VccB V Internal pins (except Enable, with WP and CD) WP, CD, Dat123.dir, CMD.dir, CMD.h, CLK.h, CLK-f, Dat0.dir, Dat0.h, Dat1.h, Dat2.h, Dat3.h 0- VccA V 1. Cout = 2.2 µF is minimum allowable capacitance value to guarantee LDO stability 2. Values for ESR include the VccB - Cout resistance path and Cout - GND resistance path. These resistance paths need to be minimized in PCB design. |
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