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ISL78420 Datasheet(PDF) 2 Page - Intersil Corporation

Part # ISL78420
Description  100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL78420 Datasheet(HTML) 2 Page - Intersil Corporation

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ISL78420
2
FN8296.1
September 24, 2012
Block Diagram
Pin Configurations
ISL78420ARTAZ
(10 LD 4X4 TDFN)
TOP VIEW
ISL78420ARTBZ
(9 LD 4X4 TDFN)
TOP VIEW
LEVEL
SHIFT
UNDER
VOLTAGE
UNDER
VOLTAGE
EPAD
DELAY
ISL78420
VDD
PWM
RDT
EN
HB
HO
HS
LO
VSS
DELAY
+
-
+
-
5V
5V
210k
EPAD
1
2
3
4
5
10
9
8
7
6
VDD
HB
HO
HS
NC
LO
VSS
PWM
EN
RDT
EPAD
1
3
4
5
10
9
8
7
6
VDD
HB
HO
HS
LO
VSS
PWM
EN
RDT
Pin Descriptions
10
LD
9
LD SYMBOL
DESCRIPTION
1
1
VDD
Positive supply voltage for lower gate driver.
Decouple this pin to ground with a 4.7µF or larger
ceramic capacitor to VSS
2
3
HB
High-side bootstrap supply voltage referenced to
HS. Connect bootstrap capacitor to this pin and HS.
3
4
HO
High-side output connected to gate of high-side FET.
4
5
HS
High-side source connect to source of high-side FET.
Connect bootstrap capacitor to this pin and HB.
8
8
PWM
PWM input. For PWM = 5V, HO = 1, LO = 0. For
PWM = 0V, HO = 0, LO = 1. For PWM = 2.5V,
HO = LO = 0.
7
7
EN
Output enable, when low, HO = LO = 0
9
9
VSS
Negative voltage supply, Connected to ground.
10 10
LO
Low-side output. Connect to gate of low-side FET.
5
-
NC
No Connect. This pin is isolated from all other pins.
May optionally be connected to VSS. Note that on
the 9 Ld package, there is no pin present at the
location normally occupied by pin 2.
6
6
RDT
A resistor connected between this pin and VSS adds
dead time by adding delay time to the falling and
rising edges of the PWM input.
-
-
EPAD
The epad is electrically isolated. It is recommended
that the epad be connected to the VSS plane for
heat removal.


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