6

Maxim Integrated

MAX19793

1500MHz to 6000MHz Dual Analog Voltage Variable

Attenuator with On-Chip 10-Bit SPI-Controlled DAC

5V AC ELECTRICAL CHARACTERISTICS (continued)

(D9, REG3) = logic 0, unless otherwise noted.) (Notes 5, 7)

Note 6: Recommended functional range. Not production tested. Operation outside this range is possible, but with degraded

performance of some parameters.

Note 7: All limits include external component losses, connectors and PCB traces. Output measurements taken at the RF port of

the Typical Application Circuit.

Note 9: Switching time measured from 50% of the CTRL signal to when the RF output settles to Q1dB (R3 = 0I).

Note 10: Switching time measured from when CS is asserted to when the RF output settles to Q1dB.

Note 11: Switching time measured from when MODE is asserted to when the RF output settles to Q1dB.

Note 12: Typical minimum time for proper SPI operation.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CTRL Switching Time (Note 9)

13dB to 0dB range

350

ns

0dB to 13dB range

730

CS Switching Time (Note 10)

14dB to 0dB range

675

ns

0dB to 14dB range

2300

MODE Switching Time (Note 11)

15dB to 0dB range (MODE 1 to 0)

700

ns

0dB to 15dB range (MODE 0 to 1)

2650

Input Return Loss

19

dB

Output Return Loss

17

dB

Group Delay

Input/output 50I lines deembedded

200

ps

Group Delay Flatness Over

125MHz Band

Peak to peak

20

ps

Group Delay Change

-120

ps

Insertion Phase Change vs.

Attenuation Control

28

Degrees

S21 Attenuation Deviation from

a Straight Line

±0.4

dB

SERIAL PERIPHERAL INTERFACE (SPI)

Maximum Clock Speed

20

MHz

Data-to-Clock Setup Time

(Note 12)

2

ns

Data-to-Clock Hold Time

(Note 12)

2.5

ns

CS-to-CLK Setup Time

(Note 12)

3

ns

CS Positive Pulse Width

(Note 12)

7

ns

Clock Pulse Width

(Note 12)

5

ns