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HT48C50-1 Datasheet(PDF) 9 Page - Holtek Semiconductor Inc |
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HT48C50-1 Datasheet(HTML) 9 Page - Holtek Semiconductor Inc |
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9 / 39 page  HT48R50A-1/HT48C50-1 Rev. 2.01 9 January 9, 2009 Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addi- tion operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the ²CLR WDT² or ²HALT² in- struction. The PDF flag can be affected only by exe- cuting the ²HALT² or ²CLR WDT² instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or exe- cuting the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can cor- rupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable or disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain inter- rupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related in- terrupt is enabled, until the SP is decremented. If immedi- ate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro- gram memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. External interrupts are triggered by a high to low transi- tion of the INT and the related interrupt request flag (EIF; bit 4 of INTC) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal Timer/Event Counter 0 interrupt is initial- ized by setting the Timer/Event Counter 0 interrupt re- quest flag (T0F; bit 5 of INTC), caused by a timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further in- terrupts. The internal timer/even counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (;bit 6 of INTC), caused by a timer 1 overflow. When the interrupt is enabled, the stack is not full and the T1F is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. Bit No. Label Function 0C C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. 1AC AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. 2 Z Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. 3OV OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. 4 PDF PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction. 5TO TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. 6~7 ¾ Unused bit, read as ²0² Status (0AH) Register |
Similar Part No. - HT48C50-1_09 |
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Similar Description - HT48C50-1_09 |
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