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HT82A525R Datasheet(PDF) 4 Page - Holtek Semiconductor Inc |
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HT82A525R Datasheet(HTML) 4 Page - Holtek Semiconductor Inc |
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4 / 71 page  Pin Description Pin Name I/O Options Description PA0/PSYNC/VSYNC PA1/PWM0 PA2/PWM1 PA3/PWM2 PA4/HSYNC PA5/PCLK PA6~PA7 I/O Pull-high (bit option) Wake-up (bit option) Bidirectional 8-bit input/output port. Each individual pin on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. The PSYNC/ VSYNC is pin shared with PA0 (dependent on PSYNC/VSYNC option). PA1~PA3 are pin-shared with PWM0~PWM2. HSYNC is pin shared with PA4 (dependent on HSYNC option). PCLK is pin shared with PA5 (dependent on PCLK option). The power supply for the I/O pins is sourced from the VDDIO pin. PB0/SCLK PB1~PB7 I/O Pull-high (bit option) CMOS/NMOS wake-up (nibble option) Bidirectional 8-bit input/output port. Each nibble on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. PB0~PB7 have CMOS/ NMOS options. SCLK is pin shared with PB0 (dependent on SCLK option). The power supply for the I/O pins is sourced from the VDDIO pin. PC0/INT PC1/TMR0 PC2/TMR1 PC3 PC4/SCS2 PC5/SCK2 PC6/SDI2 PC7/SDO2 I/O Pull-high (nibble option) wake-up (nibble option) Bidirectional I/O lines. Each nibble on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which nibble on the port have pull-high resistors. INT, TMR0, TMR1 are pin shared with PC0, PC1, PC2 respectively. SCS2 is pin shared with PC4. SCK2 is pin shared with PC5. SDI2 is pin shared with PC6. SDO2 is pin shared with PC7. The power supply for the I/O pins is sourced from the VDDIO pin. PD0/COM0/D0 PD1/COM1/D1 PD2/COM2/D2 PD3/COM3/D3 PD4/D4~PD7/D7 I/O Pull-high (nibble option) wake-up (nibble option) Bidirectional I/O lines. Each nibble on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which nibble on the port have pull-high resistors. PD0~PD3 are pin-shared with COM0~COM3. The parallel DMA data D0~D7 lines are pin shared with PD0~PD7. The power supply for the I/O pins is sourced from the VDDIO pin. PE0/SCS1 PE1/SCK1 PE2/SDI1 PE3/SDO1 PE4~PE7 I/O Pull-high (nibble option) wake-up (nibble option) Bidirectional I/O lines. Each nibble on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which nibble on the port have pull-high resistors. SCS1 is pin shared with PE0. SCK1 is pin shared with PE1. SDI1 is pin shared with PE2. SDO is pin shared with PE3. The power supply for the I/O pins is sourced from the VDDIO pin. PF0/OSCI I/O (PF0) Pull-high wake-up Bidirectional I/O line. The pin can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A configuration option determines if the pin has a pull-high resistor. The power supply for the I/O pins is sourced from the VDD pin. I(OSCI) ¾ External crystal connection Rev. 1.50 4 July 2, 2012 HT82A525R I/O Type USB 8-Bit OTP MCU with SPI |
Similar Part No. - HT82A525R_12 |
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Similar Description - HT82A525R_12 |
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