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AN11275 Datasheet(PDF) 7 Page - NXP Semiconductors |
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AN11275 Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 20 page NXP Semiconductors AN11275 SGPIO on the LPC4300 AN11275 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Application note Rev. 1 — 7 November 2012 7 of 20 Bits 6:4 determine how the output enable is controlled. The output enable can be controlled by the GPIO_OENREG register or by a different slice according to the configuration above. The output states include low or high in active mode or tri-state when disabled. In the following table the output pin multiplexing can be found. Fig 4. Table 212 of the user manual, Output pin multiplexer configuration register OUT_MUX_CFG |
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