Electronic Components Datasheet Search |
|
ADC08D502CIYB Datasheet(PDF) 9 Page - Texas Instruments |
|
ADC08D502CIYB Datasheet(HTML) 9 Page - Texas Instruments |
9 / 43 page I / O GND V A TO INTERNAL CIRCUITRY ADC08D502 www.ti.com SNOSC85 – AUGUST 2012 Converter Electrical Characteristics The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 500 MHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (1) (2) Typical Limits Units Symbol Parameter Conditions (3) (3) (Limits) STATIC CONVERTER CHARACTERISTICS DC Coupled, 1MHz Sine Wave Over INL Integral Non-Linearity ±0.3 ±0.9 LSB (max) ranged DC Coupled, 1MHz Sine Wave Over DNL Differential Non-Linearity ±0.15 ±0.6 LSB (max) ranged Resolution with No Missing Codes 8 Bits −1.5 LSB (min) VOFF Offset Error -0.45 0.5 LSB (max) VOFF_ADJ Input Offset Adjustment Range Extended Control Mode ±45 mV PFSE Positive Full-Scale Error (4) −0.6 ±25 mV (max) NFSE Negative Full-Scale Error (4) −1.31 ±25 mV (max) FS_ADJ Full-Scale Adjustment Range Extended Control Mode ±20 ±15 %FS DYNAMIC CONVERTER CHARACTERISTICS FPBW Full Power Bandwidth 1.7 GHz B.E.R. Bit Error Rate 10-18 Error/Sample Gain Flatness d.c. to 500 MHz ±0.5 dBFS fIN = 50 MHz, VIN = FSR − 0.5 dB 7.5 Bits ENOB Effective Number of Bits fIN = 100 MHz, VIN = FSR − 0.5 dB 7.5 7.1 Bits (min) fIN = 248 MHz, VIN = FSR − 0.5 dB 7.5 7.1 Bits (min) fIN = 50 MHz, VIN = FSR − 0.5 dB 47 dB SINAD Signal-to-Noise Plus Distortion Ratio fIN = 100 MHz, VIN = FSR − 0.5 dB 47 44.5 dB (min) fIN = 248 MHz, VIN = FSR − 0.5 dB 47 44.5 dB (min) fIN = 50 MHz, VIN = FSR − 0.5 dB 48 dB SNR Signal-to-Noise Ratio fIN = 100 MHz, VIN = FSR − 0.5 dB 48 45.3 dB (min) fIN = 248 MHz, VIN = FSR − 0.5 dB 47.5 45.3 dB (min) fIN = 50 MHz, VIN = FSR − 0.5 dB -55 dB THD Total Harmonic Distortion fIN = 100 MHz, VIN = FSR − 0.5 dB -55 −47.5 dB (max) fIN = 248 MHz, VIN = FSR − 0.5 dB -55 −47.5 dB (max) (1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. (2) To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally, achieving rated performance requires that the backside exposed pad be well grounded. (3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). (4) Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Transfer Characteristic Figure 2. For relationship between Gain Error and Full-Scale Error, see Specification Definitions for Gain Error. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: ADC08D502 |
Similar Part No. - ADC08D502CIYB |
|
Similar Description - ADC08D502CIYB |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |